I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC

2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010

Volumn , Issue , 2010, Pages 41-44

  Kim, Joohee ^a   Cho, Jonghyun ^a   Pak, Jun So ^a   Song, Taigon ^a   Kim, Joungho ^a   Lee, Hyungdong ^b   Lee, Junho ^b   Park, Kunwoo ^b  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

Dynamic power consumption; Interposer; Re distribution layer (RDL); Three dimensional integrated circuit (3D IC); Through Silicon Via (TSV)

Indexed keywords

ELECTRIC POWER UTILIZATION; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; LOW POWER ELECTRONICS; SILICON; TIMING CIRCUITS;

DYNAMIC POWER CONSUMPTION; INTERPOSER; RE-DISTRIBUTION; THREE DIMENSIONAL INTEGRATED CIRCUITS (3-D IC); THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 78650952214     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2010.5642539     Document Type: Conference Paper

References (5)

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3. L. Shang, et al, "Dynamic Power Consumption in Virtex™-2 FRPGQ Family," ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 2002, pp. 157-164.
4. th conference on Electrical Performance of Electronic Packaging and Systems, Portland (Tigard), Oregon, 2009, pp. 13-16.
5. F. Stellari, et al, "New Formulas of Interconnect Capacitances Based on Results of Conformal Mapping Method," IEEE Trans. Electron Devices, vol. 47, pp. 222-231, Jan. 2000.