-
1
-
-
70349652835
-
-
White Paper. University of Illinois, Champaign-Urbana, IL
-
Adve, S. et al. Parallel Computing Research at Illinois: The UPCRC Agenda. White Paper. University of Illinois, Champaign-Urbana, IL,2008; http://www. upcrc.illinois.edu/UPCRC-Whitepaper.pdf
-
(2008)
Parallel Computing Research at Illinois: The UPCRC Agenda
-
-
Adve, S.1
-
2
-
-
35648995516
-
The Landscape of Parallel Computing Research: A View from Berkeley
-
University of California, Berkeley
-
Asanovic, K. et al. The Landscape of Parallel Computing Research: A View from Berkeley. Technical Report UCB/EECS-2006-183. University of California, Berkeley, 2006; http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183. pdf
-
(2006)
Technical Report UCB/EECS-2006-183.
-
-
Asanovic, K.1
-
3
-
-
46449113366
-
Layout-accurate design and implementation of a high-throughput interconnection network for single-chip parallel processing
-
(Stanford, CA, Aug. 22-24). IEEE Press, Los Alamitos, CA
-
th Annual IEEE Symposium on High Performance Interconnects (Stanford, CA, Aug. 22-24). IEEE Press, Los Alamitos, CA, 2007.
-
(2007)
th Annual IEEE Symposium on High Performance Interconnects
-
-
Balkan, A.1
Horak, M.2
Qu, G.3
Vishkin, U.4
-
4
-
-
77954993217
-
Evolution of thread-level parallelism in desktop applications
-
ACM Press, New York
-
th Annual International Symposium on Computer Architecture (Saint-Malo, France, June 19-23). ACM Press, New York, 2010, 302-313.
-
(2010)
th Annual International Symposium on Computer Architecture (Saint-Malo, France, June 19-23).
, pp. 302-313
-
-
Blake, G.1
Dreslinski, R.2
Flautner, K.3
Mudge, T.4
-
6
-
-
77956435385
-
Resource-aware compiler prefetching for many-cores
-
IEEE Press, Los Alamitos, CA
-
Caragea, G., Tzannes, A., Keceli, F., Barua, R., and Vishkin, U. Resource-aware compiler prefetching for many-cores. In Proceedings of the Ninth International Symposium on Parallel and Distributed Computing (Istanbul, Turkey, July 7-9). IEEE Press, Los Alamitos, CA, 2010, 133-140.
-
(2010)
Proceedings of the Ninth International Symposium on Parallel and Distributed Computing (Istanbul, Turkey, July 7-9).
, pp. 133-140
-
-
Caragea, G.1
Tzannes, A.2
Keceli, F.3
Barua, R.4
Vishkin, U.5
-
7
-
-
77956435722
-
General-purpose vs. GPU: Comparison of many-cores on irregular workloads
-
University of California, Berkeley, June 14-15). Usenix, Berkeley, CA
-
Caragea, G., Keceli, F., Tzannes, A., and Vishkin, U. General-purpose vs. GPU: Comparison of many-cores on irregular workloads. In Proceedings of the Second Usenix Workshop on Hot Topics in Parallelism (University of California, Berkeley, June 14-15). Usenix, Berkeley, CA, 2010.
-
(2010)
Proceedings of the Second Usenix Workshop on Hot Topics in Parallelism
-
-
Caragea, G.1
Keceli, F.2
Tzannes, A.3
Vishkin, U.4
-
8
-
-
70449674958
-
Performance potential of an easy-to-program PRAM-on-chip prototype versus state-of-the-art processor
-
(Calgary, Canada, Aug. 11-13). ACM Press, New York
-
st ACM SPAA Symposium on Parallelism in Algorithms and Architectures (Calgary, Canada, Aug. 11-13). ACM Press, New York, 2009, 163-165.
-
(2009)
st ACM SPAA Symposium on Parallelism in Algorithms and Architectures
, pp. 163-165
-
-
Caragea, G.1
Saybasili, B.2
Wen, X.3
Vishkin, U.4
-
9
-
-
0004116989
-
-
MIT Press Cambridge, MA
-
Cormen, T., Leiserson, C., Rivest, R., and Stein, C. Introduction to Algorithms, Third Edition. MIT Press, Cambridge, MA, 2009.
-
(2009)
Introduction to Algorithms, Third Edition.
-
-
Cormen, T.1
Leiserson, C.2
Rivest, R.3
Stein, C.4
-
11
-
-
0008757016
-
The queue-read queue-write asynchronous PRAM model
-
Apr.
-
Gibbons, P., Matias, Y., and Ramachandran, V. The queue-read queue-write asynchronous PRAM model. Theoretical Computer Science 196, 1-2 (Apr. 1998), 3-29.
-
(1998)
Theoretical Computer Science
, vol.196
, Issue.1-2
, pp. 3-29
-
-
Gibbons, P.1
Matias, Y.2
Ramachandran, V.3
-
12
-
-
0020705129
-
The NYU ultracomputer designing an MIMD shared-memory parallel computer
-
Feb.
-
Gottlieb, A. et al. The NYU ultracomputer designing an MIMD shared-memory parallel computer. IEEE Transactions on Computers 32, 2 (Feb. 1983), 175-189.
-
(1983)
IEEE Transactions on Computers
, vol.32
, Issue.2
, pp. 175-189
-
-
Gottlieb, A.1
-
13
-
-
55949104267
-
Case study of gate-level logic simulation on an extremely fne-grained chip multiprocessor
-
Apr.
-
Gu, P. and Vishkin, U. Case study of gate-level logic simulation on an extremely fne-grained chip multiprocessor. Journal of Embedded Computing 2, 2 (Apr. 2006), 181-190.
-
(2006)
Journal of Embedded Computing
, vol.2
, Issue.2
, pp. 181-190
-
-
Gu, P.1
Vishkin, U.2
-
14
-
-
52049104934
-
A pilot study to compare programming effort for two parallel programming models
-
Nov.
-
Hochstein, L., Basili, V., Vishkin, U., and Gilbert, J. A pilot study to compare programming effort for two parallel programming models. Journal of Systems and Software 81, 11 (Nov. 2008), 1920-1930.
-
(2008)
Journal of Systems and Software
, vol.81
, Issue.11
, pp. 1920-1930
-
-
Hochstein, L.1
Basili, V.2
Vishkin, U.3
Gilbert, J.4
-
15
-
-
77955101700
-
A low-overhead asynchronous interconnection network for gals chip multiprocessor
-
(Grenoble, France, May 3-6). IEEE Computer Society, Washington D.C.
-
Horak, M., Nowick, S., Carlberg, M., and Vishkin, U. A low-overhead asynchronous interconnection network for gals chip multiprocessor. In Proceedings of the Fourth ACM/IEEE International Symposium on Networks-on-Chip (Grenoble, France, May 3-6). IEEE Computer Society, Washington D.C., 2010, 43-50.
-
(2010)
Proceedings of the Fourth ACM/IEEE International Symposium on Networks-on-Chip
, pp. 43-50
-
-
Horak, M.1
Nowick, S.2
Carlberg, M.3
Vishkin, U.4
-
17
-
-
0003857183
-
-
Wiley-Interscience, New York
-
Keller, J., Kessler, C., and Traeff, J. Practical PRAM Programming. Wiley-Interscience, New York, 2001.
-
(2001)
Practical PRAM Programming.
-
-
Keller, J.1
Kessler, C.2
Traeff, J.3
-
18
-
-
78650851293
-
-
U.S. Patent 6 768 336
-
Nuzman, J. and Vishkin, U. Circuit Architecture for Reduced-Synchrony-On- Chip Interconnect. U.S. Patent 6,768,336, 2004; http://patft.uspto.gov/netacgi/ nph-Parser?Sect1=PTO2&Sect2=HITOFF&p= 1&u= %2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1 &f=G&l=50&co1= AND&d=PTXT&s1=6768336.PN.&O S=PN/6768336&RS=PN/6768336
-
(2004)
Circuit Architecture for Reduced-Synchrony-On-Chip Interconnect
-
-
Nuzman, J.1
Vishkin, U.2
-
19
-
-
85032559815
-
The trouble with multi-core: Chipmakers are busy designing microprocessors that most programmers can't handle
-
July
-
Patterson, D. The trouble with multi-core: Chipmakers are busy designing microprocessors that most programmers can't handle. IEEE Spectrum (July 2010).
-
(2010)
IEEE Spectrum
-
-
Patterson, D.1
-
21
-
-
34548083281
-
The free lunch is over: A fundamental shift towards concurrency in software
-
Mar.
-
Sutter, H. The free lunch is over: A fundamental shift towards concurrency in software. Dr. Dobb's Journal 30, 3 (Mar. 2005).
-
(2005)
Dr. Dobb's Journal
, vol.30
, pp. 3
-
-
Sutter, H.1
-
22
-
-
77952220812
-
Is teaching parallel algorithmic thinking to high school students possible? One teacher's experience
-
(Milwaukee, WI, Mar. 10-13). ACM Press, New York
-
Torbert, S., Vishkin, U., Tzur, R., and Ellison, D. Is teaching parallel algorithmic thinking to high school students possible? One teacher's experience. In Proceedings of the 41st ACM Technical Symposium on Computer Science Education (Milwaukee, WI, Mar. 10-13). ACM Press, New York, 2010, 290-294.
-
(2010)
Proceedings of the 41st ACM Technical Symposium on Computer Science Education
, pp. 290-294
-
-
Torbert, S.1
Vishkin, U.2
Tzur, R.3
Ellison, D.4
-
23
-
-
77957656725
-
Lazy binary splitting: A run-time adaptive dynamic works-stealing scheduler
-
(Bangalore, India, Jan. 9-14). ACM Press, New York
-
Tzannes, A., Caragea, G., Barua, R., and Vishkin, U. Lazy binary splitting: A run-time adaptive dynamic works-stealing scheduler. In Proceedings of the15th ACM Symposium on Principles and Practice of Parallel Programming (Bangalore, India, Jan. 9-14). ACM Press, New York, 2010, 179-189.
-
(2010)
Proceedings of the15th ACM Symposium on Principles and Practice of Parallel Programming
, pp. 179-189
-
-
Tzannes, A.1
Caragea, G.2
Barua, R.3
Vishkin, U.4
-
24
-
-
57849138004
-
A bridging model for multi-core computing
-
(Karlruhe, Germany, Sept. 15-17). Lecture Notes in Computer Science 5193. Springer, Berlin
-
Valiant, L. A bridging model for multi-core computing. In Proceedings of the European Symposium on Algorithms (Karlruhe, Germany, Sept. 15-17). Lecture Notes in Computer Science 5193. Springer, Berlin, 2008, 13-28.
-
(2008)
Proceedings of the European Symposium on Algorithms
, pp. 13-28
-
-
Valiant, L.1
-
25
-
-
78650823017
-
-
U.S Patents 6 463,527; 6,542,918; 7,505,822; 7,523,293; 7,707, 388, 2002-2010
-
Vishkin, U. U.S. Patents 6,463,527; 6,542,918; 7,505,822; 7,523,293; 7,707,388, 2002-2010; http://patft.uspto.gov/
-
-
-
Vishkin, U.1
-
26
-
-
77950973754
-
Algorithmic approach to designing an easy-to-program system: Can it lead to a hardware-enhanced programmer's workfow add-on?
-
(Lake Tahoe CA Oct. 4-7). IEEE Computer Society Washington D.C.
-
Vishkin, U. Algorithmic approach to designing an easy-to-program system: Can it lead to a hardware-enhanced programmer's workfow add-on? In Proceedings of the 27th International Conference on Computer Design (Lake Tahoe, CA, Oct. 4-7). IEEE Computer Society, Washington D.C., 2009, 60-63.
-
(2009)
Proceedings of the 27th International Conference on Computer Design
, pp. 60-63
-
-
Vishkin, U.1
-
27
-
-
46449103865
-
Models for advancing PRAM and other algorithms into parallel programs for a PRAM-on-chip platform
-
S. Rajasekaran and J. Reif, Eds. Chapman and Hall/CRC Press, Boca Raton, FL
-
Vishkin, U., Caragea, G., and Lee, B. Models for advancing PRAM and other algorithms into parallel programs for a PRAM-on-chip platform. In Handbook on Parallel Computing, S. Rajasekaran and J. Reif, Eds. Chapman and Hall/CRC Press, Boca Raton, FL, 2008, 51-60.
-
(2008)
Handbook on Parallel Computing
, pp. 51-60
-
-
Vishkin, U.1
Caragea, G.2
Lee, B.3
-
28
-
-
56749182827
-
FPGA-based prototype of a PRAM-on-chip processor
-
(Ischia, Italy, May 5-7). ACM Press, New York
-
Wen, X. and Vishkin, U. FPGA-based prototype of a PRAM-on-chip processor. In Proceedings of the Fifth ACM Conference on Computing Frontiers (Ischia, Italy, May 5-7). ACM Press, New York, 2008, 55-66.
-
(2008)
Proceedings of the Fifth ACM Conference on Computing Frontiers
, pp. 55-66
-
-
Wen, X.1
Vishkin, U.2
|