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Volumn , Issue , 2009, Pages 60-63

Algorithmic approach to designing an easy-to-program system: Can it lead to a hW-enhanced programmer's workflow add-on?

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMIC APPROACH; ALGORITHMICS; COMPUTATION MODEL; GRADUATE STUDENTS; HARDWARE AND SOFTWARE; HARDWARE SUPPORTS; MANY-CORE; MULTITHREADED; ON CHIPS; OPEN-ENDED QUESTIONS; PARALLEL SORTING ALGORITHMS; PARALLEL SYSTEM; PERFORMANCE TUNING; PRAM MODELS; PROGRAM SYSTEMS; WORKFLOW MODULES;

EID: 77950973754     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413174     Document Type: Conference Paper
Times cited : (3)

References (20)
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    • Stanford, CA
    • A. O. Balkan, M. Horak, G. Qu, and U. Vishkin. Layout-accurate design and implementation of a high-throughput interconnection network for single-chip parallel processing. In Hot Interconnects, Stanford, CA, 2007.
    • (2007) Hot Interconnects
    • Balkan, A.O.1    Horak, M.2    Qu, G.3    Vishkin, U.4
  • 5
    • 51549119170 scopus 로고    scopus 로고
    • An area-efficient highthroughput hybrid interconnection network for single-chip parallel processing
    • Anaheim, CA, June
    • A. O. Balkan, G. Qu, and. U. Vishkin. An Area-Efficient HighThroughput Hybrid Interconnection Network for Single-Chip Parallel Processing. In 45th Design Automation Conference, Anaheim, CA, June 8-13, 2008.
    • (2008) 45th Design Automation Conference , pp. 8-13
    • Balkan, A.O.1    Qu, G.2    Vishkin, U.3
  • 6
    • 70449674958 scopus 로고    scopus 로고
    • Performance potential of an easy-to-program PRAM-On-Chip prototype versus state-of-the-art processor
    • Calgary, Canada
    • G. Caragea, B. Saybasili, X. Wen, and. U. Vishkin. Performance potential of an easy-to-program PRAM-On-Chip prototype versus state-of-the-art processor. In Proc. ACM. SPAA, Calgary, Canada, 2009.
    • (2009) Proc. ACM. SPAA
    • Caragea, G.1    Saybasili, B.2    Wen, X.3    Vishkin, U.4
  • 10
    • 55949104267 scopus 로고    scopus 로고
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    • P. Gu and U. Vishkin. Case study of gate-level logic simulation on an extremely fine-grained chip multiprooesor. J. Embedded Comp., 2:181-190, 2006.
    • (2006) J. Embedded Comp. , vol.2 , pp. 181-190
    • Gu, P.1    Vishkin, U.2
  • 14
    • 0346863310 scopus 로고
    • An O((n2)log n) parallel max-flow algorithm
    • Y. Shiloach and U. Vishkin. An O((n**2)log n) parallel max-flow algorithm. J. Algorithms, 3(2): 128-146, 1982.
    • (1982) J. Algorithms , vol.3 , Issue.2 , pp. 128-146
    • Shiloach, Y.1    Vishkin, U.2
  • 17
    • 55949135962 scopus 로고    scopus 로고
    • Models for advancing PRAM and other algorithms into parallel programs for a PRAM.-On-Chip platform
    • Editors: S. Rajasekaran and J. Reif. CRC press
    • U. Vishkin, G. Caragea, and B. Lee. Models for advancing PRAM and other algorithms into parallel programs for a PRAM.-On-Chip platform. In Handbook, of Parallel Computing: Models, Algorithms and Applications. Editors: S. Rajasekaran and J. Reif. CRC press, 2008.
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  • 19
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    • Keynote presentation, CS4HS Workshop, Carnegie-Mellon University, July power point presentation available though the XMT home page
    • U. Vishkin, R. Tzur, D. Ellison and G.C. Caragea. Parallel programming for High. Schools. Keynote presentation, CS4HS Workshop, Carnegie-Mellon University, July 2009, power point presentation available though the XMT home page.
    • (2009) Parallel Programming for High Schools
    • Vishkin, U.1    Tzur, R.2    Ellison, D.3    Caragea, G.C.4
  • 20
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    • FPGA-based prototype of a PRAM-on-chip processor
    • Ischia, Italy, May
    • X. Wen and. U. Vishkin. FPGA-based prototype of a PRAM-on-chip processor, ACM Computing Frontiers, Ischia, Italy, May 5-7, 2008.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.