-
1
-
-
58149159197
-
Configuration of floorplan and placement algorithm using horizontal and vertical contour based on single sequence
-
Kang, L., Juebang, Y., Yongbing, Y.: Configuration of floorplan and placement algorithm using horizontal and vertical contour based on single sequence. In: International conference on Communications, Circuits and Systems, pp. 1171-1174 (2008)
-
(2008)
International Conference on Communications, Circuits and Systems
, pp. 1171-1174
-
-
Kang, L.1
Juebang, Y.2
Yongbing, Y.3
-
2
-
-
0342647395
-
A GA with heuristic based decode for IC floorplanning
-
Gwee, B.H., Lim, M.H.: A GA with heuristic based decode for IC floorplanning. Integration, the VLSI Journal 28(2), 157-172 (1999)
-
(1999)
Integration, the VLSI Journal
, vol.28
, Issue.2
, pp. 157-172
-
-
Gwee, B.H.1
Lim, M.H.2
-
3
-
-
47649085779
-
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning
-
Fernando, P., Katkoori, S.: An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning. In: 21st International Conference on VLSI Design, pp. 337-342 (2008)
-
(2008)
21st International Conference on VLSI Design
, pp. 337-342
-
-
Fernando, P.1
Katkoori, S.2
-
4
-
-
0032690067
-
An O-tree representation of non-slicing floorplan and its applications
-
Guo, P.N., Cheng, C.K., Yoshimura, T.: An O-tree representation of non-slicing floorplan and its applications. In: Proceedings of the 36th ACM/IEEE conference on Design automation conference, New Orleans, Louisiana, United States, pp. 268-273 (1999)
-
(1999)
Proceedings of the 36th ACM/IEEE Conference on Design Automation Conference, New Orleans, Louisiana, United States
, pp. 268-273
-
-
Guo, P.N.1
Cheng, C.K.2
Yoshimura, T.3
-
5
-
-
0034855935
-
TCG:A transitive closure gragh-based representation for non-slicing floorplans
-
Lin, J.M., Chang, Y.W.: TCG:A transitive closure gragh-based representation for non-slicing floorplans. In: Proc. DAC, pp. 764-769 (2001)
-
(2001)
Proc. DAC
, pp. 764-769
-
-
Lin, J.M.1
Chang, Y.W.2
-
6
-
-
0033704928
-
An enhanced perturbing algorithm for floorplan design using the O-tree representation
-
Pang, Y., Cheng, C.K., Yoshimura, T.: An enhanced perturbing algorithm for floorplan design using the O-tree representation. In: The Proceedings of ACM International Physical Design Symposia, pp. 168-173 (2000)
-
(2000)
The Proceedings of ACM International Physical Design Symposia
, pp. 168-173
-
-
Pang, Y.1
Cheng, C.K.2
Yoshimura, T.3
-
8
-
-
3142756516
-
Handling Multiple Objectives with Particle Swarm Optimization
-
Coello, C.A.C., Pulido, G.T., Lechuga, M.S.: Handling Multiple Objectives With Particle Swarm Optimization. IEEE Trans. on Evol. Comput. 8, 256-279 (2004)
-
(2004)
IEEE Trans. on Evol. Comput.
, vol.8
, pp. 256-279
-
-
Coello, C.A.C.1
Pulido, G.T.2
Lechuga, M.S.3
-
10
-
-
52149121158
-
An evolutionary particle swarm algorithm for multi-objective optimisation
-
Minyou, C., Chuansheng, W., Peter, F.: An evolutionary particle swarm algorithm for multi-objective optimisation. In: Proceedings of 7th World congress on Intellgent Control and Automation, pp. 3269-3274 (2008)
-
(2008)
Proceedings of 7th World Congress on Intellgent Control and Automation
, pp. 3269-3274
-
-
Minyou, C.1
Chuansheng, W.2
Peter, F.3
-
11
-
-
58149242173
-
A discrete particle swarm optimization algorithm for the multiobjective permutation flowshop sequencing problem
-
Wenzhong, G., Guolong, C., Min, H., Shuili, C.: A discrete particle swarm optimization algorithm for the multiobjective permutation flowshop sequencing problem. In: Proceedings of the second international conference of Fuzzy Information and Engineering, pp. 323-331 (2007)
-
(2007)
Proceedings of the Second International Conference of Fuzzy Information and Engineering
, pp. 323-331
-
-
Wenzhong, G.1
Guolong, C.2
Min, H.3
Shuili, C.4
-
12
-
-
3142768423
-
Self-Organizing Hierarchical Particle Swarm Optimizer with Time-Varying Acceleration Coefficients
-
Ratnaweera, A., Halgamuge, S.K.: Self-Organizing Hierarchical Particle Swarm Optimizer With Time-Varying Acceleration Coefficients. IEEE Transactions on Evolutionary Computation 8(3), 240-255 (2004)
-
(2004)
IEEE Transactions on Evolutionary Computation
, vol.8
, Issue.3
, pp. 240-255
-
-
Ratnaweera, A.1
Halgamuge, S.K.2
-
13
-
-
0034481271
-
Corner Block List:An effective and efficient topological representation of non-slicing floorplan
-
Hong, X., Huang, G., Cai, Y., Gu, J., Dong, S., Cheng, C.K., Gu, J.: Corner Block List:An effective and efficient topological representation of non-slicing floorplan. In: Proc. ICCAD, pp. 8-12 (2000)
-
(2000)
Proc. ICCAD
, pp. 8-12
-
-
Hong, X.1
Huang, G.2
Cai, Y.3
Gu, J.4
Dong, S.5
Cheng, C.K.6
Gu, J.7
-
14
-
-
0030378255
-
VLSI module placement based on rectangle-packing by the sequence-pair
-
PII S0278007096094134
-
Murata, H., Fujiyoshi, K., Nakatake, S., Kajitani, Y.: VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair. IEEE Trans. on CAD 15(12), 1518-1524 (1996) (Pubitemid 126780413)
-
(1996)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.15
, Issue.12
, pp. 1518-1524
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
15
-
-
0032090672
-
Module Packing Based on the BSG-Structure and IC Layout Applications
-
Nakatake, S., Fujiyoshi, K., Murata, H., Kajitani, Y.: Module Packing Based on the BSG-Structure and IC Layout Applications. IEEE Trans. on CAD 17(6), 519-530 (1998)
-
(1998)
IEEE Trans. on CAD
, vol.17
, Issue.6
, pp. 519-530
-
-
Nakatake, S.1
Fujiyoshi, K.2
Murata, H.3
Kajitani, Y.4
-
16
-
-
7944224006
-
VLSI Floorplanning Method Based on Genetic Algorithms
-
Wang, X.G., Yao, L.S., Gan, J.R.: VLSI Floorplanning Method Based on Genetic Algorithms. Chinese Journal of Semiconductors 23(3), 330-335 (2002)
-
(2002)
Chinese Journal of Semiconductors
, vol.23
, Issue.3
, pp. 330-335
-
-
Wang, X.G.1
Yao, L.S.2
Gan, J.R.3
-
17
-
-
54049089606
-
A nonlinear optimization methodology for VLSI fixed-outline floorplannin
-
Chaomin, L., Anjos, M.F., Vannelli, A.: A nonlinear optimization methodology for VLSI fixed-outline floorplannin. J. Comb. Optim. 16, 378-401 (2008)
-
(2008)
J. Comb. Optim.
, vol.16
, pp. 378-401
-
-
Chaomin, L.1
Anjos, M.F.2
Vannelli, A.3
|