A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS

ESSCIRC 2010 - 36th European Solid State Circuits Conference

Volumn , Issue , 2010, Pages 370-373

  Sundström, Timmy ^a   Svensson, Christer ^a   Alvandpour, Atila ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; BUILDING BLOCKES; CLOCKING SCHEMES; CMOS TECHNOLOGY; CRITICAL PATHS; EFFECTIVE NUMBER OF BITS; GENERAL PURPOSE; HIGH-SPEED; NYQUIST; NYQUIST BAND; OPEN LOOPS; PIPELINE ADCS; PIPELINE CONVERTERS; SAMPLE RATE; SINGLE CHANNELS; SINGLE-CHANNEL;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS;

PIPELINES;

EID: 78650403404     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2010.5619720     Document Type: Conference Paper

References (5)

1. D.-L. Shen, T.-C. Lee, "A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 258-268, Mar 2007.
2. A. Varzaghani, C.-K.K. Yang, "A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization," in IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 901-915, Mar 2009.
3. A. Nazemi, et al., "A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS," in IEEE Symposium on VLSI Circuits Dig. Tech. Papers, pp. 18-19, June 2008.
4. T. Sundström, B. Murmann, and C. Svensson, "Power dissipation bounds for high-speed Nyquist analog-to-digital converters," in IEEE Transactions on Circuits and Systems I, Regular Papers, vol. 56, no. 3, pp. 509-518, Mar. 2009.
5. A. Verma, B. Razavi, "A 10-Bit 500-MS/s 55-mW CMOS ADC," in IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 3039-3050, Mar 2009.