A 6-bit 800-MS/s pipelined A/D converter with open-loop amplifiers

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 2, 2007, Pages 258-268

  Shen, Ding Lan ^a,b   Lee, Tai Cheng ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Analog digital conversion; CMOS analog integrated circuits; Gain control

Indexed keywords

TWO-BANK-INTERLEAVED ARCHITECTURE; VOLTAGE-MODE OPEN-LOOP AMPLIFIERS;

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; GAIN CONTROL; POWER AMPLIFIERS;

ANALOG TO DIGITAL CONVERSION;

EID: 33847754746     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.889380     Document Type: Article

References (19)

1. A. Varzaghani and C.-K. K. Yang, "A 600 Ms/s 5-bit pipelined analog-to-digital converter for serial-link applications," in Symp. VLSI Circuits Dig. Tech. Papers, 2004, pp. 276-279.
2. M. Choi and A. A. Abidi, "A 6-bit 1.3-Gsample/s A/D converter in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, Dec. 2001.
3. X. Jiang and M.-C. Frank, "A 1-GHz signal bandwidth 6-bit CMOS with power efficient averaging," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 532-535, Feb. 2005.
4. B. Murmann and B. E. Boser, "A 12-bit 75 Ms/s pipelined ADC using open-loop residue amplifier," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
5. K. Poulton, R. Neff, A. Muto, W. Liu, A. Burstein, and M. Heshami, "A 4 Gsample/s 8b ADC in 0.35 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2002, vol., pp. 166-457.
6. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montijo, "A 20 Gs/s 8 b ADC with a 1 MB memory in 0.18 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2003, vol. , pp. 318-319.
7. D. Draxelmay, "A 6 b 600 MHz 10 mW ADC array in digital 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 264-265.
8. J. Goes, J. C. Vital, and J. E. Franca, "Systematic design for optimization of high-speed self-calibrated pipelined A/D converters," IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 45, no. 12, pp. 1513-1526, Dec. 1998.
9. B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke, "A CMOS 13-bit cyclic RSD A/D converter," IEEE J. Solid-State Circuits, vol. 27, no. 7, pp. 957-965, Jul. 1992.
10. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.
11. C. S. G. Conroy, D. W. Cline, and P. R. Gray, "An 8-bit 85-ms/s parallel pipeline A/D converter in 1-μm CMOS," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 447-454, Apr. 1993.
12. D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, "A digital background calibration technique for time-interleaved analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1904-1911, Dec. 1998.
13. K. C. Dyer, D. Fu, S. H. Lewis, and P. J. Hurst, "An analog background calibration technique for time-interleaved analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1912-1919, Dec. 1998.
14. B. Xia, A. Valdes-Garcia, and E. Sanchez-Sinencio, "A 10-bit 44-Ms/s 20 mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 530-539, Mar. 2006.
15. P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001.
16. G. Geelen, "A 6 b 1.1 Gsample/s CMOS A/D converter," in IEEE ISSCC Dig. Tech. Papers, 2001, pp. 128-129.
17. C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, "A 6-bit 1.2-Gs/s low-power flash-ADC in 0.13-μm digital CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1499-1505, Jul. 2005.
18. K. Uyttenhove and M. S. J. Steyaert, "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1115-1122, Jul. 2003.
19. P. C. S. Scholtens and M. Vertregt, "A 6-bit 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1599-1609, Dec. 2002.