A customized design of DRAM controller for on-chip 3D DRAM stacking

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Zhang, Tao ^a   Wang, Kui ^b   Feng, Yi ^b   Song, Xiaodi ^b   Duan, Lian ^a   Xie, Yuan ^a   Cheng, Xu ^b   Lin, Youn Long ^c  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b PEKING UNIVERSITY   (China)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3D MEMORY; 3D STACKING; ACCESS LATENCY; ACCESS POLICIES; BONDING TECHNOLOGY; DATA BANDWIDTH; DOUBLE DATA RATE; DRAM CHIPS; HIGH BANDWIDTH; I/O PINS; IC TECHNOLOGY; LAYER 2; LOW POWER; MEMORY WALL; ON CHIP MEMORY; ON CHIPS; SDRAM CONTROLLERS; SIMULATION RESULT; SINGLE CHANNELS; THREE-DIMENSIONAL (3D); THROUGH SILICON VIAS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; CONTROLLERS; DESIGN; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; THREE DIMENSIONAL; WALLS (STRUCTURAL PARTITIONS);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 78649882774     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617465     Document Type: Conference Paper

References (9)

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