An FPGA-based accelerator for analog VLSI Artificial Neural Network emulation

Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010

Volumn , Issue , 2010, Pages 771-778

  Van Liempd, Barend ^a   Herrera, Daniel ^b   Figueroa, Miguel ^b  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b UNIVERSITY OF CONCEPCIÓN   (Chile)

Author keywords

Analog VLSI emulation; Artificial Neural Networks; Embed ded systems; FPGA based accelerators; Hardware time multiplexing

Indexed keywords

ANALOG VLSI; ARTIFICIAL NEURAL NETWORK; ARTIFICIAL NEURAL NETWORKS; DATA FLOW; DESKTOP COMPUTER; DEVICE MISMATCH; FPGA-BASED ACCELERATORS; HARDWARE RESOURCES; HIGH COSTS; MEMORY SYSTEMS; NETWORK SIZE; NONLINEAR TRANSFER FUNCTIONS; ON CHIPS; SINGLE-NEURON; SOFTWARE IMPLEMENTATION; TEST SAMPLES; TEST SEQUENCE; TIME MULTIPLEXING;

ANALOG CIRCUITS; COMPUTER HARDWARE; DESIGN; HARDWARE; LINEAR ACCELERATORS; MULTIPLEXING; NETWORK ARCHITECTURE; NETWORK PERFORMANCE; NETWORKS (CIRCUITS); RANDOM ACCESS STORAGE; SYSTEMS ANALYSIS; VLSI CIRCUITS;

NEURAL NETWORKS;

EID: 78649877784     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2010.20     Document Type: Conference Paper

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