Design and characterization of an SEU-robust register in 130nm CMOS for application in HEP ASICs

Journal of Instrumentation

Volumn 5, Issue 11, 2010, Pages

  Bonacini, S ^a  

^a CERN   (Switzerland)

Author keywords

Digital electronic circuits; Front end electronics for detector readout; Radiation damage to electronic components; Radiation hard electronics

Indexed keywords

D-FLIP-FLOP; DETECTOR READOUT; DIGITAL ELECTRONIC CIRCUITS; ELECTRONIC COMPONENT; RADIATION-HARD; STANDARD LIBRARIES;

RADIATION DAMAGE;

ION BEAMS;

EID: 78649872640     PISSN: 17480221     EISSN: 17480221     Source Type: Journal    
DOI: 10.1088/1748-0221/5/11/C11019     Document Type: Conference Paper

References (6)

1. F. Faccio and G. Cervelli, Radiation-induced edge effects in deep submicron CMOS transistors, IEEE Trans. Nucl. Sci. 52 (2005) 2413.
2. T. Calin, M. Nicolaidis, and R. Velazco, Upset Hardened Memory Design for Submicron CMOS Technology, IEEE Trans. Nucl. Sci. 43 (1996) 2874.
3. S. Bonacini, K. Kloukinas, and A. Marchioro, Development of SEU-robust, radiation-tolerant and industry-compatible programmable logic components, 2007 JINST 2 P09009.
4. S. Buchner, M. Baze, D. Brown, D. McMorrow and J. Melinger, Comparison of error rates in combinational and sequential logic, IEEE Trans. Nucl. Sci. 44 (1997) 2209.
5. S. Bonacini, F. Faccio, K. Kloukinas and A. Marchioro, An SEU-robust Configurable Logic Block for the Implementation of a Radiation-Tolerant FPGA, IEEE Trans. Nucl. Sci. 53 (2006) 3408.
6. M. Huhtinen and F. Faccio, Computational method to estimate Single Event Upset rates in an accelerator environment, Nucl. Instrum. Meth. A 450 (2000) 155.