A 10b 120MS/s 45nm CMOS ADC using a re-configurable three-stage switched Op-Amp

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Kim, Young Ju ^a   Lee, Kyung Hoon ^a   Ji, Seung Hak ^a   Kwon, Yi Gi ^a   Lee, Seung Hoon ^a   Moon, Kyoung Jun ^a   Choi, Michael ^a   Park, Ho Jin ^b   Park, Byeong Ha ^a  

^a Sogang University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS ADC; CMOS PROCESSS; DIE AREA; MEMORY EFFECTS; MULTI-PATH; PIPELINE ADCS; RE-CONFIGURABLE; SAMPLING NETWORK; SINGLE-ENDED; SINUSOIDAL INPUT; SWITCHED AMPLIFIERS; THREE-STAGE AMPLIFIERS; ZERO CANCELLATION;

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 78649864561     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617409     Document Type: Conference Paper

References (8)

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