Analytical delay variation modeling for evaluating sub-threshold synchronous/asynchronous designs

Proceedings of the 8th IEEE International NEWCAS Conference, NEWCAS2010

Volumn , Issue , 2010, Pages 69-72

  Lin, Tong ^a   Chong, Kwen Siong ^a   Gwee, Bah Hwee ^a   Chang, Joseph S ^a   Qiu, Zhao Xiang ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ADDER CIRCUIT; DELAY MARGIN; DELAY VARIATION; LARGE DELAYS; MODELING ERRORS; PROCESS , VOLTAGE AND TEMPERATURES; PVT VARIATIONS; QUASI DELAY INSENSITIVE; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; SYNCHRONOUS/ASYNCHRONOUS; TIMING MARGIN;

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER SIMULATION; DIGITAL CIRCUITS; THRESHOLD ELEMENTS; TIME DELAY; TIMING CIRCUITS;

DELAY CIRCUITS;

EID: 78349292952     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2010.5603925     Document Type: Conference Paper

References (12)

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