Moths: Mobile threads for on-chip networks

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2010, Pages 541-542

  Misler, Matthew ^a   Enright Jerger, Natalie ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

chip multiprocessors; on chip networks

Indexed keywords

PARALLEL ARCHITECTURES; ROUTERS;

AVERAGE PACKET LATENCIES; CHIP MULTIPROCESSOR; LONG DISTANCE COMMUNICATION; NETWORK-ON-CHIP(NOC); ON-CHIP NETWORKS; THREAD MIGRATION; TRAFFIC PATTERN; TRAFFIC VOLUMES;

NETWORK-ON-CHIP;

EID: 78149240348     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1854273.1854342     Document Type: Conference Paper

References (5)

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5. U. Ogras and R. Marculescu, "Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach," in Proceedings of DATE, March 2005.