High-linearity CMOS T/R switch design above 20 GHz using asymmetrical topology and AC-floating bias

IEEE Transactions on Microwave Theory and Techniques

Volumn 57, Issue 1, 2009, Pages 948-956

  Park, Piljae ^a   Shin, Dong Hun ^a   Yue, C Patrick ^a  

^a University of California   (United States)

Author keywords

1 dB compression point; AC floating biasing technique; Asymmetrical transmit receive (T R) switch topology; T R switch; Triple well (TW) CMOS

Indexed keywords

1DB COMPRESSION POINT; BIASING TECHNIQUES; T/R SWITCH; TRANSMIT/RECEIVE SWITCHES; TRIPLE WELL;

BANDPASS FILTERS; CMOS INTEGRATED CIRCUITS; DIGITAL CONTROL SYSTEMS; LINEARIZATION; TOPOLOGY;

ELECTRIC SWITCHES;

EID: 77958107906     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

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