Modeling of triple-well isolation and the loading effects on circuits up to 50 GHz

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 217-220

  Park, Piljae ^a   Yue, C Patrick ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Substrate noise isolation; Triple well bias; Triple well model

Indexed keywords

BIAS RESISTORS; BIASING CONDITIONS; CIRCUIT PERFORMANCES; CMOS TECHNOLOGIES; COMPACT MODELS; LOADING EFFECTS; NMOS DEVICES; NOISE FREQUENCIES; NOISE ISOLATIONS; OUTPUT IMPEDANCES; QUANTITATIVE ANALYSES; SERIES RESISTANCES; SOURCE AND DRAINS; SUBSTRATE IMPEDANCES; SUBSTRATE LOADINGS; SUBSTRATE NOISE ISOLATION; TEST CIRCUITS; TRIPLE-WELL BIAS; TRIPLE-WELL MODEL;

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); TRIODES;

SUBSTRATES;

EID: 57849165070     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672062     Document Type: Conference Paper

References (5)

1. Vinella, R.M. et al, "Substrate Noise Isolation Experiments in a 0.18-μm 1P6M Triple-well CMOS process on a Lightly Doped Substrate," 2007 IEEE Instrumentation and Measurement Technology Conference, May 2007, pp. 1-6
2. Barbier-Petot, C., Bardy, S., Biard, C., Descamps, P., "Substrate isolation in 90nm RF-CMOS technology," European Microwave Conference, Oct. 2005, pp. 4-7.
3. Tung-Sheng Chen et al, "An efficient noise isolation technique for SOC application," IEEE Transaction on Electron Devices, Feb. 2004, pp. 255-260
4. Mei-Chao Yeh. et al, "Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance," IEEE Transactions on Microwave Theory and Techniques, Volume 54, Issue 1, Jan. 2006, pp. 31-39.
5. Piljae Park, Dong Hun Shin, John J. Pekarik, Mark Rodwell, C. Patrick Yue, "A High-linearity, LC-tuned, 24-GHz T/R switch in 90-nm CMOS," to be presented at IEEE Radio Frequency Integrated Circuits Symposium, June 2008.