An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits

Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010

Volumn , Issue , 2010, Pages 71-76

  Maliuk, Dzmitry ^a   Stratigopoulos, Haralampos G ^b   Makris, Yiorgos ^a  

^a Yale University   (United States)

^b CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG VLSI; BUTTERWORTH FILTER; COMPUTATIONAL TIME; FAULTY CIRCUITS; HARDWARE NEURAL NETWORKS; LOW-POWER CONSUMPTION; MULTI LAYER PERCEPTRON; PROOF OF CONCEPT; RE-CONFIGURABLE; TRAINING ALGORITHMS; WEIGHT PERTURBATION;

ANALOG CIRCUITS; FACE RECOGNITION; IIR FILTERS; INTEGRATED CIRCUIT TESTING; NEURAL NETWORKS; OPERATIONAL AMPLIFIERS; SIMULATED ANNEALING; TOPOLOGY; VLSI CIRCUITS;

BUILT-IN SELF TEST;

EID: 77957989014     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2010.5560230     Document Type: Conference Paper

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