Verification of bounded delay asynchronous circuits with timed traces

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1548, Issue , 1998, Pages 59-73

  Yoneda, Tomohiro ^a   Zhou, Bin ^a   Schlingloff, Bernd Holger ^b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b UNIVERSITY OF BREMEN   (Germany)

Author keywords

Asynchronous circuits; Computer aided verification; Conformance checking; Delay analysis; Failure analysis; Hardware verification; Real time systems; State space exploration; Time petri nets; Trace theory

Indexed keywords

ALGEBRA; ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER AIDED ANALYSIS; COMPUTER HARDWARE; DELAY CIRCUITS; FAILURE ANALYSIS; INTERACTIVE COMPUTER SYSTEMS; PETRI NETS; RECONFIGURABLE HARDWARE; SEMANTICS; SOFTWARE ENGINEERING; SPACE RESEARCH; SPECIFICATIONS;

ASYNCHRONOUS CIRCUITS; COMPUTER AIDED VERIFICATIONS; CONFORMANCE CHECKING; DELAY ANALYSIS; HARDWARE VERIFICATION; STATE SPACE EXPLORATION; TIME PETRI NETS; TRACE THEORY;

REAL TIME SYSTEMS;

EID: 84959017757     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-49253-4_7     Document Type: Conference Paper

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