Reliability constraints for TANOS memories due to alumina trapping and leakage

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 966-969

  Amoroso, Salvatore M ^a,b   Mauri, Aurelio ^b   Galbiati, Nadia ^b   Scozzari, Claudia ^b   Mascellino, Evelyne ^a   Camozzi, Elisa ^b   Rangoni, Armando ^b   Ghilardi, Tecla ^b   Grossi, Alessandro ^b   Tessariol, Paolo ^b   Compagnoni, Christian Monzio ^a   Maconi, Alessandro ^a   Lacaita, Andrea L ^a,c   Spinelli, Alessandro S ^a,c   Ghidini, Gabriella ^b  

^a POLITECNICO DI MILANO   (Italy)

^b Numonyx   (Italy)

^c IFN CNR   (Italy)

Author keywords

Charge trapping memories; Flash memories; High k dielectrics; Semiconductor device modeling

Indexed keywords

ALUMINA THICKNESS; CHARGE STORAGE; CHARGE TRAPPING MEMORIES; DE-TRAPPING; HIGH-K DIELECTRICS; LEAKAGE PATHS; MEMORY RELIABILITY; MODELING RESULTS; PROGRAM AND ERASE; RELIABILITY CONSTRAINTS; SATURATION LEVELS; SEMICONDUCTOR DEVICE MODELING; THRESHOLD INSTABILITY; TRAP PARAMETERS;

ALUMINUM; ELECTRIC FIELDS; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR SWITCHES;

FLASH MEMORY;

EID: 77957583502     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488694     Document Type: Conference Paper

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