Leveraging cost matrix structure for hardware implementation of stereo disparity computation using dynamic programming

Computer Vision and Image Understanding

Volumn 114, Issue 11, 2010, Pages 1126-1138

  MacLean, W James ^a   Sabihuddin, Siraj ^a   Islam, Jamin ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b RYERSON UNIVERSITY   (Canada)

Author keywords

Dynamic programming; Field programmable gate arrays; Hardware; Pipeline processing; Real time systems; Stereo disparity

Indexed keywords

COMPUTING COST; COST MATRICES; ENERGY MINIMISATION; FRAME-RATE; HARDWARE IMPLEMENTATIONS; HARDWARE SOLUTIONS; HIGH FRAME RATE; IMAGE SIZES; IMPROVED METHODS; LARGE DISPARITY; PIPELINE PROCESSING; PIPELINED ARCHITECTURE; STEREO DISPARITY; TIMING REQUIREMENTS;

COMPUTER HARDWARE; COMPUTER PROGRAMMING; COMPUTER VISION; COSTS; HARDWARE; LOGIC GATES; MATRIX ALGEBRA; MAXIMUM LIKELIHOOD; PIPELINE PROCESSING SYSTEMS; PIXELS; REAL TIME SYSTEMS; STEREO VISION;

DYNAMIC PROGRAMMING;

EID: 77957344553     PISSN: 10773142     EISSN: 1090235X     Source Type: Journal    
DOI: 10.1016/j.cviu.2010.03.011     Document Type: Conference Paper

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