A massively parallel digital learning processor

Advances in Neural Information Processing Systems 21 - Proceedings of the 2008 Conference

Volumn , Issue , 2009, Pages 529-536

  Graf, Hans Peter ^a   Cadambi, Srihari ^a   Durdanovic, Igor ^a   Jakkula, Venkata ^a   Sankardadass, Murugan ^a   Cosatto, Eric ^a   Chakradhar, Srimat ^a  

^a NEC LABORATORIES AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

E-LEARNING; ELECTRIC LOSSES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LEARNING ALGORITHMS; LEARNING SYSTEMS; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; NEURAL NETWORKS;

DIGITAL-LEARNING; FIELD PROGRAMMABLES; MACHINE LEARNING ALGORITHMS; MASSIVELY PARALLELS; ORDERS OF MAGNITUDE; PERFORMANCE; PROCESSING ELEMENTS; PROGRAMMABLE GATE ARRAY; VARIABLE RESOLUTION; VECTOR PROCESSING;

PARALLEL ARCHITECTURES;

EID: 77954282436     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Ramacher, et al. (1995) Synapse-1: A high-speed general purpose parallel neurocomputer system. In Proc. 9th Intl. Symposium on Parallel Processing (IPPS'95), pp. 774-781.
2. Asanovic, K., Beck, Feldman, J., Morgan, N. & Wawrzynek, J. (1994) A Supercomputer for Neural Computation, Proc. IEEE Intl. Joint Conference on Neural Networks, pp. 5-9, Orlando, Florida.
3. Neil, P., (2005) Combining hardware with a powerful automotive MCU for powertrain applications. In Industrial Embedded Resource Guide, p. 88.
4. th KES 2003, Oxford, pp 169-176. (Pubitemid 37142721)
5. Murasaki, M., Arima, Y. & Shinohara, H. (1993) A 20 Tera-CPS Analog Neural Network Board. In Proc. Int. Joint Conf. Neural Networks, pp. 3027 - 3030.
6. Pedersen, R., Schoeberl, M. (2006), An Embedded Support Vector Machine, WISE 2006.
7. Dey, S., Kedia, M. Agarwal, N., Basu, A., Embedded Support Vector Machine: Architectural Enhancements and Evaluation, in Proc 20th Int. Conf. VLSI Design.
8. Anguita, D., Boni, A., Ridella, S., (2003) A Digital Architecture for Support Vector Machines: Theory, Algorithm, and FPGA Implementation, IEEE Trans. Neural Networks, 14/5, pp.993-1009.
9. Chu, C., Kim, S., Lin, Y., Yu, Y., Bradski, G., Ng, A. & Olukotun, K. (2007) Map-Reduce for Machine Learning on Multicore, Advances in Neural Information Processing Systems 19, MIT Press.
10. Catanzaro, B., Sundaram, N., & Keutzer, K. (2008) Fast Support Vector Machine Training and Classification on Graphics Processors, Proc. 25th Int. Conf. Machine Learning, pp 104-111.
11. Durdanovic, I., Cosatto, E. & Graf, H. (2007) Large Scale Parallel SVM Implementation. In L. Bottou, O. Chapelle, D. DeCoste, J. Weston (eds.), Large Scale Kernel Machines, pp. 105-138, MIT Press.
12. Simard, P & Graf, H. (1994) Backpropagation without Multiplication. In J. Cowan, G. Tesauro, J. Alspector, (eds.), Neural Information Processing Systems 6, pp. 232 - 239, Morgan Kaufmann.
13. Savich, A., Moussa, M., Areibi, S., (2007) The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study, IEEE Trans. Neural Networks, 18/1, pp. 240-252. (Pubitemid 46062930)