Digital time-optimal phase shedding in multiphase buck converters

IEEE Transactions on Power Electronics

Volumn 25, Issue 9, 2010, Pages 2242-2247

  Costabeber, A ^a   Mattavelli, P ^a   Saggini, S ^b  

^a UNIVERSITY OF PADOVA   (Italy)

^b UNIVERSITY OF UDINE   (Italy)

Author keywords

DC DC converters; digital control; field programmable gate array (FPGA); multiphase converters; phase shedding (PS)

Indexed keywords

CURRENT LEVELS; DIGITAL CONTROL; DIGITAL CONTROLLERS; DUTY CYCLES; EXPERIMENTAL TEST; FEED-FORWARD; LIGHT LOADS; MINIMUM TIME; MULTIPHASE BUCK CONVERTER; MULTIPHASE CONVERTERS; PHASE SHEDDING (PS); POWER STAGE; SYNCHRONOUS BUCK CONVERTER; TIME-OPTIMAL; TRANSIENT TIME; VOLTAGE DEVIATIONS;

DC POWER TRANSMISSION; DIGITAL CONTROL SYSTEMS; ELECTRIC CONVERTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; OPTIMIZATION;

DC-DC CONVERTERS;

EID: 77956926577     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2010.2049374     Document Type: Article

References (12)

1. B. Oraw and R. Ayyanar, "Multivariable analysis of VR controllers with load line regulation and phase current balancing," in Proc. IEEE APEC 2008, Feb. 24-28, pp. 1728-1734.
2. P. Zumel, C. Fernandez, A. de Castro, and O. Garcia, "Efficiency improvement in multiphase converter by changing dynamically the number of phases," in Proc. IEEE Proc. PESC 2006, Jun., pp. 1-6.
3. Y. Panov and M. Jovanovic, "Design considerations for 12V/1.5V, 50A voltage regulator modules," IEEE Trans. Power Electron., vol. 16, no. 6, pp. 776-783, Nov. 2001.
4. K. Yao, K. Lee, M. Xu, and F. C. Lee, "Optimal design of the active droop control method for the transient response," in Proc. IEEE Appl. Power Electron. Conf. Expo. (APEC), Feb. 9-13, 2003, vol. 3, pp. 718-723.
5. K. Yao, Y. Ren, J. Sun, K. Lee, M. Xu, J. Zhou, and F. C. Lee, "Adaptive voltage position design for voltage regulators," in Proc. 19th IEEE Appl. Power Electron. Conf. Expo. (APEC), 2004, vol. 1, pp. 272-278.
6. B. Patella, A. Prodic, A. Zirger, and D. Maksimovic, "High-frequency digital PWM controller IC for DC-DC Converters," IEEE Trans. Power Electron., vol. 18, no. 1, pp. 438-446, Jan. 2003.
7. A. V. Peterchev and S. R. Sanders, "Quantization resolution and limit cycling in digitally controlled PWM converters," IEEE Trans. Power Electron., vol. 18, no. 1, pp. 301-308, Jan. 2003.
8. A. Costabeber, L. Corradini, S. Saggini, and P. Mattavelli, "Time-optimal, parameters-insensitive digital controller for DC-DC buck converters," in Proc. 39th IEEE Power Electron. Spec. Conf. (PESC), Rhodes, Jun. 2008, pp. 1243-1249.
9. Santa C. Huerta, A. Cobos, A. D. Castro, and O. Garcia, "FPGA based pulse width modulators with time resolution under 2 ns," in Proc. IEEE Power Electron. Spec. Conf., APEC 2007, Feb. 25-Mar. 1, pp. 877-881.
10. K. Y.-C. Wang and Y.-Y. Tzou, "Design and realization of a digital multiphase-interleaved VRM controller using FPGA," in Proc. IEEE Ind. Electron. Soc. (IECON), Nov. 5-8, 2007, pp. 1978-1982.
11. A. D. Castro and E. Todorovich, "DPWM based on FPGA clock phase shifting with time resolution under 100 ps," in Proc. IEEE Power Electron. Spec. Conf. (PESC), 2008, pp. 3054-3059.
12. Y. Liyu, F. J. Fan, and A. Q. Huang, "Controller design issues and solutions for buck converters with phase shedding and AVP functions," in Proc. Energy Convers. Congr. Expo. (ECCE), Sep. 20-24, 2009, pp. 2862-2868.