Spec based flip-flop and buffer insertion

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 270-275

  Akkiraju, Nataraj ^a   Mohan, Mosur ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; COMPUTER SIMULATION; DYNAMIC PROGRAMMING; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE;

AUTOMATIC REPEATER INSERTION TOOL; PRUNING RULES; SPEC BASED FLOP INSERTION ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0344551080     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. Cocchini. Simultaneous insertion of repeaters and flip-flops in high performance vlsi circuits. In Proc. International Conference on CAD, 2002.
2. S. Hassoun, C. J. Alpert, and M. Thiagarajan. Optimal buffered routing path constructions for single and multiple clock domain systems. In Proc. International Conference on CAD, 2002.
3. J. Lillis, C. K. Cheng, and T. T. Lin. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid-State Circuits, 31(3):437-447, 1996.
4. R. Lu, G. Zhong, C. K. Koh, and K. Y. Chao. Flip-flop and repeater insertion for early interconnect planning. In Proc. Design Automation and Test in Europe Conference (DATE), pages 690-695, 2002.
5. L. P. P. P. van Ginneken. Buffer placement in distributed rc-tree networks for minimal elmore delay. In Proc. International Symposium on Circuits and Systems, pages 865-868, 1990.