Leveraging delay slack in flip-flop and buffer insertion for power reduction

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 69-74

  Simonson, Lucanus ^a   Tam, King Ho ^a   Akkiraju, Nataraj ^b   Mohan, Mosur ^b   He, Lei ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DYNAMIC PROGRAMMING; ESTIMATION; MATHEMATICAL MODELS; OPTIMIZATION; POLYNOMIALS; PROBLEM SOLVING;

DRIVE RESISTANCE; POWER CONSUMPTION; POWER REDUCTION; TOPOLOGY GENERATION;

FLIP FLOP CIRCUITS;

EID: 2942672730     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2004.1283652     Document Type: Conference Paper

References (8)

1. N. Akkiraju and M. Mohan. Spec based flip-flop and buffer insertion. In Proc. Int. Conf. on Computer Aided Design, 2003.
2. K. Banerjee and A. Mehrotra. Power dissipation issues in interconnect performance optimization for sub-180 nm designs. In Proceedings of 2002 Symposium on VLSI Circitus, 2002.
3. K. Boese, A. Kahng, B. McCoy, and G. Robins. Fidelity and near-optimality of Elmore-based routing constructions. In Proc. IEEE Int. Conf. on Computer Design, pages 81-84, 1993.
4. A. P. Chandrakasan and R. W. Brodersen. Low power digital CMOS design. Kluwer Academic Publishers, 1995.
5. P. Cocchini. Simultaneous insertion of repeaters and flip-flops in high performance vlsi circuits. In Proc. Int. Conf. on Computer Aided Design, 2002.
6. L. He and W. Liao. Full-chip interconnect power estimation and simulation considering concurrent repeater and flip-flip insertion. In Proc. Int. Conf. on Computer Aided Design, 2003.
7. J. Lillis, C. K. Cheng, and T.-T. Lin. Optimal wire sizing and buffer insertion for low power and a generalized delay model. In Proc. Int. Conf. on Computer Aided Design, pages 138-143, 1995.
8. L. P. P. P. van Ginneken. Buffer placement in distributed RC-tree networks for minimal Elmore delay. In Proc. IEEE Int. Symp. on Circuits and Systems, pages 865-868, 1990.