Detecting tangled logic structures in VLSI netlists

Proceedings - Design Automation Conference

Volumn , Issue , 2010, Pages 603-608

  Jindal, Tanuj ^a   Alpert, Charles J ^b   Hu, Jiang ^a   Li, Zhuo ^b   Nam, Gijoon ^b   Winn, Charles B ^c  

^a TEXAS A AND M UNIVERSITY   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c IBM   (United States)

Author keywords

Clustering; Congestion prediction; Rent rule; Tangled logic

Indexed keywords

CLUSTERING; CONGESTION PREDICTION; CONVENTIONAL CIRCUITS; DATA PATHS; HOTSPOTS; LARGE GROUPS; LOGIC STRUCTURES; NETLIST; PROBLEM COMPLEXITY; PULL OUT; RENT RULE; RENT'S RULE; SMALL GROUPS; TANGLED LOGIC;

COMPUTER AIDED DESIGN; FORECASTING;

NETWORK ROUTING;

EID: 77956216388     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1837274.1837422     Document Type: Conference Paper

References (12)

1. T. Chen, T. Hsu, Z. Jiang, Y. Chang. NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. In Proceedings of the International Symposium on Physical Degisn, pages 236-238, 2005.
2. T. Chan, J. Cong, J. Shinnerl, K. Sze, M. Xie. mPL6: enhanced multilevel mixed-size placement. In Proceedings of the 2006 International Symposium on Physical Design, pages 212-214, 2006.
3. C. J. Alpert, A. B. Kahng, G.-J. Nam, S. Reda, and P. Villarrubia. A semi-persistent clustering technique for VLSI circuit placement. In Proceedings of the ACM International Symposium on Physical Design, pages 200-207, 2005.
4. C. J. Alpert and A. B. Kahng. Recent directions in netlist partitioning: a survey. Integration: the VLSI Journal, 19(1-2):1-81, 1995.
5. P. K. Chan, M. D. F. Schlag, and J. Y. Zien. Spectral K-way ratio-cut partitioning and clustering. In Proceedings of the ACM/IEEE Design Automation Conference, pages 749-754, 1993.
6. T.-K. Ng, J. Oldfield, and V. Pitchumani. Improvements of a mincut partition algorithm. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 470-473, 1987.
7. Lars Hagen, Andrew B. Kahng A New Approach to Effective Circuit Clustering In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 422-427, 1992.
8. J. Garbers, H. J. Promel, and A. Steger. Finding clusters in VLSI circuits. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 520-523, 1990.
9. J. Cong and S. K. Lim. Edge separability-based circuit clustering with application to multilevel circuit partitioning. IEEE Transactions on Computer-Aided Design, 23(3):346-357, March 2004.
10. P. Kudva, A. Sullivan, and W. Dougherty. Metrics for structural logic synthesis. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 551-556, 2002.
11. C. J. Alpert and A. B. Kahng. A general framework for vertex orderings with applications to circuit clustering. IEEE Transactions on VLSI Systems, 4(2):240-246, June 1996.
12. G.-J. Nam, C. J. Alpert, and P. G. Villarrubia. ISPD 2005/2006 Placement Benchmarks, pages 3-12. Springer, 2007.