-
1
-
-
0024091885
-
A variable delay line PLL for CPU coprocessor synchronization
-
Oct.
-
M.G. Johnson and E.L. Hudson, "A variable delay line PLL for CPU coprocessor synchronization,"' IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1218-1223, Oct. 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, Issue.5
, pp. 1218-1223
-
-
Johnson, M.G.1
Hudson, E.L.2
-
3
-
-
0030235194
-
Asynchronous FPGA architectures
-
Sept.
-
R. Payne, "Asynchronous FPGA architectures," IEEE Proc.-Comput. Digit. Tech., vol. 143, no. 5, pp. 282-286, Sept. 1996.
-
(1996)
IEEE Proc.-Comput. Digit. Tech.
, vol.143
, Issue.5
, pp. 282-286
-
-
Payne, R.1
-
4
-
-
0028743754
-
An asynchronous pipelined lattice structure filter
-
U.V. Cummings, A.M. Lines, and A.J. Martin, "An asynchronous pipelined lattice structure filter," IEEE Sump. Adv. Res. Asynchronous Circuits Syst., Salt Lake City, UT, Nov. 3-5, 1994, pp. 126-133.
-
IEEE Sump. Adv. Res. Asynchronous Circuits Syst., Salt Lake City, UT, Nov. 3-5, 1994
, pp. 126-133
-
-
Cummings, U.V.1
Lines, A.M.2
Martin, A.J.3
-
5
-
-
0142185445
-
Continuous-time digital signal processing
-
16 Oct.
-
Y. Tsividis, "Continuous-time digital signal processing", Electronic Letters, vol. 39, no. 21, pp. 1551-1551, 16 Oct. 2003.
-
(2003)
Electronic Letters
, vol.39
, Issue.21
, pp. 1551-1551
-
-
Tsividis, Y.1
-
6
-
-
56849098704
-
A Continuous-Time ADC/DSP/DAC System with No Clock and with Activity-Dependent Power Dissipation
-
B. Schell, and Y. Tsividis, "A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation," IEEE J. of Solid-State Circuits, vol. 43, no. 11, pp 2472-2481, 2008.
-
(2008)
IEEE J. of Solid-State Circuits
, vol.43
, Issue.11
, pp. 2472-2481
-
-
Schell, B.1
Tsividis, Y.2
-
7
-
-
0030195866
-
A low-voltage, low-power CMOS delay element
-
July
-
G. Kim, "A low-voltage, low-power CMOS delay element,", IEEE J. of Solid-State Circuits, vol. 31, no. 7, pp. 966-971, July 1996.
-
(1996)
IEEE J. of Solid-State Circuits
, vol.31
, Issue.7
, pp. 966-971
-
-
Kim, G.1
-
8
-
-
42649099628
-
A low power tunable delay element suitable for asynchronous delays of burst information
-
May
-
B. Schell and Y. Tsividis, "A low power tunable delay element suitable for asynchronous delays of burst information," IEEE J. of Solid-State Circuits, vol. 43, no.5, pp. 1227-1234, May 2008.
-
(2008)
IEEE J. of Solid-State Circuits
, vol.43
, Issue.5
, pp. 1227-1234
-
-
Schell, B.1
Tsividis, Y.2
-
9
-
-
0036976596
-
Comparison and analysis of delay elements
-
N. Mahapatra, A. Tareen, and S. Garimella, "Comparison and analysis of delay elements," Proc. MWACAS, 2002, vol. II, pp.473-476.
-
Proc. MWACAS, 2002
, vol.2
, pp. 473-476
-
-
Mahapatra, N.1
Tareen, A.2
Garimella, S.3
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