Optimization of a 45nm CMOS voltage controlled oscillator using design of experiments

2006 IEEE Region 5 Conference

Volumn , Issue , 2006, Pages 87-90

  Sarivisetti, Gayathri ^a   Kougianos, Elias ^a   Mohanty, Saraju P ^a   Palakodety, Atmaram ^a   Ale, Anil Kumar ^a  

^a UNIVERSITY OF NORTH TEXAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; CMOS INTEGRATED CIRCUITS; DESIGN OF EXPERIMENTS; ELECTRON TUNNELING; OSCILLISTORS; VARIABLE FREQUENCY OSCILLATORS;

CENTER FREQUENCY; DESIGN PARAMETERS; FUNCTIONAL SPECIFICATION; GATE OXIDE THICKNESS; GATE TUNNELING CURRENTS; NANO-METER REGIMES; NANOMETER DESIGN; OPTIMIZATION GOALS;

INTEGRATED CIRCUIT DESIGN;

EID: 77955592411     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TPSD.2006.5507456     Document Type: Conference Paper

References (14)

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