Quantifying LER to predict its impact on BEOL TDDB reliability at 20nm 1/2 pitch

2010 IEEE International Interconnect Technology Conference, IITC 2010

Volumn , Issue , 2010, Pages

  Demuynck, S ^a   Roussel, Ph ^a   Stucchi, M ^a   Versluijs, J ^a   Gishia, G G ^a   De Roest, D ^b   Tokei, Zs ^a   Beyer, G P ^a  

^a IMEC   (Belgium)

^b ASM BELGIUM   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CU/LOW-K INTERCONNECTS; DOUBLE PATTERNING; IN-LINE; INTEGRATION SCHEME; K SPACE; ORDERS OF MAGNITUDE; REFINED MODEL; TDDB LIFETIME; WAFER LEVEL;

FORECASTING;

EID: 77955590836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2010.5510698     Document Type: Conference Paper

References (5)

1. ITRS roadmap 2007 edition
2. M. Stucchi and Zs. Tocombining double acute accentkei, "Impact of LER and via misalignment on the electric field between nanometer-scale wires, IEEE IITC, San Francisco, CA, 2008, pp: 174-176
3. Zs. Tocombining double acute accentkei et al., "Impact of LER on BEOL reliability: a quantitative model and experimental validation", IEEE IITC, Sapporo, Japan, 2009, pp: 228-230
4. S. Demuynck et al., "Integration and dielectric reliability of 30nm 1/2 pitch structures in Aurora® LK HM", in press
5. A. Yamaguchi, D. Ryuzaki, K. Takeda and H. Kawada, "Evaluation of line-edge roughness in Cu/low-k interconnect patterns with CD-SEM", IITC Proc. (2009), IEEE IITC, Sapporo, Japan, 2009, pp: 225-227