Optimized TSV process using bottom-up electroplating without wafer cracks

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1642-1646

  Lim, Byeong Ok ^a   Choi, Kwang Seong ^a   Eom, Yong Sung ^a   Bae, Hyun Cheol ^a   Jung, Sunghae ^a   Sung, Ki Jun ^b   Moon, Jong Tae ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^b University of Science and Technology (UST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER LAYERS; BOTTOM-UP ELECTROPLATING; CARRIER WAFERS; CU ELECTROPLATING; CUTTING PROCESS; DRIE PROCESS; FLIP-CHIP BONDING; OXIDE LAYER; PROCESS COSTS; SEM; SOLDER BUMP; SOLDER POWDERS; THINNING PROCESS; WAFER EDGE; WAFER SIZES; WAFER THINNING;

COST REDUCTION; CRACKS; CUTTING; DESCALING; ELECTROPLATING; FLIP CHIP DEVICES; GOLD COATINGS; RESINS; SOLDERING; SOLDERING ALLOYS;

WAFER BONDING;

EID: 77955216805     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490762     Document Type: Conference Paper

References (5)

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