Locality-driven parallel power grid optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 28, Issue 1, 2009, Pages 1190-1200

  Zeng, Zhiyu ^a   Li, Peng ^a  

^a Texas AandM University   (United States)

Author keywords

Locality; Optimization; Parallel; Power grid; Wire sizing

Indexed keywords

DISTRIBUTION NETWORK; DIVIDE AND CONQUER; HIERARCHICAL OPTIMIZATION; IR DROP; LARGE POWER; LOCALITY OPTIMIZATION; NETWORK COMPLEXITY; PARALLEL POWER; PARALLELIZATIONS; POWER GRIDS; SIZING OPTIMIZATION; WIRE SIZING; WIRING AREA;

DISTRIBUTED PARAMETER NETWORKS; POWER GENERATION; WIRE;

OPTIMIZATION;

EID: 77955184666     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (17)

1. H. H. Chen and D. D. Ling, "Power supply noise analysis methodology for deep-submicron VLSI chip designs," in Proc. IEEE/ACM DAC, 1997, pp. 638-643.
2. S. R. Nassif and J. N. Kozhaya, "Fast power grid simulation," in Proc. IEEE/ACM DAC, 2000, pp. 156-161.
3. J. N. Kozhaya, S. R. Nassif, and F. N. Najm, "A multi-grid like technique for power grid analysis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 10, pp. 1148-1160, Oct. 2002.
4. M. Zhao, R. Panda, S. S. Sapatnekar, and D. Blaauw, "Hierarchical analysis of power distribution networks," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 2, pp. 159-168, Feb. 2002.
5. H. Su, E. Acar, and S. R. Nassif, "Power grid reduction based on algebraic multigrid principles," in Proc. IEEE/ACM DAC, 2003, pp. 109-112.
6. H. Qian, S. R. Nassif, and S. S. Sapatnekar, "Random walks in a supply network," in Proc. IEEE/ACM DAC, 2003, pp. 93-98.
7. E. Chiprout, "Fast flip-chip power grid analysis via locality and grid shells," in Proc. IEEE/ACM ICCAD, 2004, pp. 485-488.
8. I. A. Ferzli, F. N. Najm, and L. Kruse, "A geometric approach for early power grid verification using current constraints," in Proc. IEEE/ACM ICCAD, 2007, pp. 40-47.
9. X. D. S. Tan, C. J. R. Shi, and J. C. Lee, "Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 12, pp. 1678-1684, Dec. 2003.
10. K. Wang and M. Marek-Sadowska, "On-chip power supply network optimization using multigrid-based technique," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 3, pp. 407-417, Mar. 2005.
11. J. Singh and S. S. Sapatnekar, "Partition-based algorithm for power grid design using locality," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 4, pp. 664-677, Apr. 2007.
12. S. Borkar, "Thousand core chips - A technology perspective," in Proc. IEEE/ACM DAC, 2007, pp. 746-749.
13. R. Dutta and M. Marek-Sadowska, "Automatic sizing of power/ground (P/G) networks in VLSI," in Proc. IEEE/ACM DAC, 1989, pp. 783-786.
14. A. Wächter and L. T. Biegler, "On the implementation of a primaldual interior point filter line search algorithm for large-scale nonlinear programming," Math. Program., vol. 106, no. 1, pp. 25-57, May 2006.
15. A. Wächter, C. Visweswariah, and A. R. Conn, "Large-scale nonlinear optimization in circuit tuning," Future Gener. Comput. Syst., vol. 21, no. 8, pp. 1251-1262, Oct. 2005.
16. X. Wu, X. Hong, Y. Cai, Z. Luo, C. K. Cheng, J. Gu, and W.W. M. Dai, "Area minimization of power distribution network using efficient nonlinear programming techniques," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 7, pp. 1086-1094, Jul. 2004.
17. A. Berman and R. J. Plemmons, Nonnegative Matrices in the Mathematical Sciences. Philadelphia, PA: SIAM, 1994.