NXP system-in-package vision and latest 3D technology developments

Advancing Microelectronics

Volumn 34, Issue 6, 2007, Pages 16-21

  Yannou, J M ^a   Neuilly, F ^a   Moreno, J A ^a   Pommier, M ^a   Bellenger, S ^a   Biermans, P ^a  

^a NXP SEMICONDUCTORS   (France)

Author keywords

3D vertical integration; Passive integration; SiP; Through silicon vias; Wafer level packaging

Indexed keywords

CELLULAR RADIO SYSTEMS; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; INNOVATION; INTEGRATED CIRCUITS; INTERNET PROTOCOLS; MICROELECTRONICS; NETWORKS (CIRCUITS); PROGRAMMABLE LOGIC CONTROLLERS; SYSTEMS ANALYSIS; TECHNOLOGICAL FORECASTING;

3D TECHNOLOGY; 3D VERTICAL INTEGRATION; ANALOGUE CIRCUITS; APPLICATIONS.; BUILDING BLOCKS; FUTURE TECHNOLOGIES; INNOVATION PROJECTS; MICRO-ELECTRO-MECHANICAL; PASSIVE COMPONENTS; PASSIVE INTEGRATION; ROAD MAPS; SIP; SIP TECHNOLOGY; SOC SOLUTIONS; SOC TECHNOLOGY; SYSTEM IN PACKAGING; SYSTEM INTEGRATION; TECHNOLOGY DEVELOPMENTS; THROUGH SILICON VIAS; VERTICAL INTEGRATION; VIRTUAL PROTOTYPING; WAFER-LEVEL PACKAGING;

TECHNOLOGY;

EID: 48849102922     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (4)

1. D. Chevrie, "A silicon-based System-in-Package technology," 15th European Microelectronics and Packaging Conference (EMPC), Brugge, Belgium, June 12-15, 2005.
2. A. Mangrum, "Packaging Technologies for Mobile Platforms," 2006 Electronics Packaging Technology Conference (EPTC), Singapore, December 6-8, 2006.
3. M. Brunnbauer, "Embedded Wafer Level Ball Grid Array," 2006 Electronics Packaging Technology Conference (EPTC), Singapore, December 6-8, 2006.
4. N. Strusevich, "Modeling the behavior of solder joints for Wafer-Level SiP," 2006 Electronics Packaging Technology Conference (EPTC), Singapore, December 6-8, 2006.