Characterization of silicon die strength with application to die crack analysis

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2008, Pages

  Guojun, Hu ^a   Jing En, Luan ^a   Baraton, Xavier ^a  

^a STMICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP ARRAYS; DIE AREA; DIE CRACKING; DIE CRACKS; DIE FAILURE; DIE STRENGTH; DIE STRESS; ELECTRONIC PACKAGE; FAILURE STRENGTH; FINITE ELEMENT ANALYSIS; MANUFACTURING PROCESS; PACKAGE SIZE; PERFORMANCE REQUIREMENTS; RELIABILITY PROBLEMS; ROOM TEMPERATURE; SEMICONDUCTOR PACKAGES; SILICON DIE; SURFACE CONDITIONS; TEMPERATURE COEFFICIENT OF EXPANSIONS; TEST METHOD; THERMAL MISMATCH; THERMOMECHANICAL DEFORMATIONS;

ATOMIC FORCE MICROSCOPY; CHIP SCALE PACKAGES; CRACKS; FINITE ELEMENT METHOD; PACKAGING; QUALITY ASSURANCE;

DIES;

EID: 77955110550     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMT.2008.5507873     Document Type: Conference Paper

References (6)

1. Tsai, M. Y., and Lin, C. S., "Determination of Silicon Die Strength," Proc 55th Electron. Comp. Technol. Conf, 2005, pp. 1155-1162.
2. McLellan, N., Fan, N., Liu, S., Lau, K., and Wu, J., "Effect of Wafer Thinning Condition on the Roughness, Morphology and Fracture Strength of Silicon Die," ASME J. Electron. Packag., Vol. 126 (2004), pp. 110-114.
3. Yeung, B. H., Hause, V., and Lee, T. Y. T., "Assessment of Backside Processes Through Die Strength Evaluation," IEEE Trans. Adv. Packag., Vol. 23, No. 3 (2000), pp. 582-587.
4. Cook, R. D., and Young, W. C., 1985, Advanced Mechanics of Materials, Macmillan, New York.
5. Kelly, N.H. MacMillan, Strong Solids, 3rd edn, Oxford Science, Oxford, 1986, pp. 382.
6. D.Y.R. Chong, W.E. Lee, J.H.L. Pang, T.H. Low, B.K. Lim, "Mechanical Characterization in Failure Strength of Silicon Dice", Proc Inter Society Conference on Thermal Phenomena, ITherm, Nevada, USA, June 2004, pp. 203-210.