Ultra fine-grained run-time power gating of on-chip routers for CMPs

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2010, Pages 61-68

  Matsutani, Hiroki ^a   Koibuchi, Michihiro ^b   Ikebuchi, Daisuk ^c   Usami, Kimiyoshi ^d   Nakamura, Hiroshi ^a   Amano, Hideharu ^c  

^a UNIVERSITY OF TOKYO   (Japan)

^b NATIONAL INSTITUTE OF INFORMATICS   (Japan)

^c KEIO UNIVERSITY   (Japan)

^d SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PERFORMANCE; COMPONENT BASED; LEAKAGE POWER; ON CHIPS; ON-CHIP NETWORKS; OPTIMAL LEVEL; POWER GATINGS; POWER SUPPLY; RUNTIMES; ULTRA-FINES; WAKE-UP LATENCY;

CIRCUIT SIMULATION; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS;

ROUTERS;

EID: 77955109876     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.16     Document Type: Conference Paper

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