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Volumn 7, Issue 2, 1999, Pages 183-190

Data parallel-fault simulation

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING; LOGIC GATES; PARALLEL PROCESSING SYSTEMS;

EID: 0032679387     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.766745     Document Type: Article
Times cited : (22)

References (18)
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    • Waicukauski, J.A.1
  • 3
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    • Accelerated fault simulation and fault grading in combinational circuits
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    • K. J. Antriech and M. H. Schulz, "Accelerated fault simulation and fault grading in combinational circuits," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 704-711, Sept. 1987.
    • (1987) IEEE Trans. Computer-Aided Design , vol.CAD-6 , pp. 704-711
    • Antriech, K.J.1    Schulz, M.H.2
  • 4
    • 0004959808 scopus 로고
    • Paris: A parallel pattern fault simulator for synchronous sequential circuits
    • N. Gouders and R. Kaibel, "Paris: A parallel pattern fault simulator for synchronous sequential circuits," in Proc. ICCAD, 1991.
    • (1991) Proc. ICCAD
    • Gouders, N.1    Kaibel, R.2
  • 5
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    • Proofs: A fast memory efficient sequential circuit fault simulator
    • Feb.
    • T. M. Nierman, W. T. Cheng, and J. H. Patel, "Proofs: A fast memory efficient sequential circuit fault simulator," IEEE Trans. Computer-Aided Design, vol. 11, pp. 198-207, Feb. 1992.
    • (1992) IEEE Trans. Computer-Aided Design , vol.11 , pp. 198-207
    • Nierman, T.M.1    Cheng, W.T.2    Patel, J.H.3
  • 6
    • 0027658725 scopus 로고
    • Parallel concurrent fault simulation
    • Sept.
    • D. G. Saab, "Parallel concurrent fault simulation," IEEE Trans. VLSI Syst., vol. 1, pp. 356-363, Sept. 1993.
    • (1993) IEEE Trans. VLSI Syst. , vol.1 , pp. 356-363
    • Saab, D.G.1
  • 7
    • 0029213265 scopus 로고
    • Vision: An efficient parallel pattern fault simulator for synchronous sequential circuits
    • R. Nair and D. S. Ha, "Vision: An efficient parallel pattern fault simulator for synchronous sequential circuits," in Proc. IEEE VLSI Test Symp. Dig., 1995, pp. 221-226.
    • (1995) Proc. IEEE VLSI Test Symp. Dig. , pp. 221-226
    • Nair, R.1    Ha, D.S.2
  • 10
    • 0026818473 scopus 로고
    • Fault simulation on massively parallel SIMD machines algorithms, implementations and results
    • V. Narayanan and V. Pitchumani, "Fault simulation on massively parallel SIMD machines algorithms, implementations and results," J. Electron. Testing: Theory Applicat., no. 3, pp. 79-92, 1992.
    • (1992) J. Electron. Testing: Theory Applicat. , Issue.3 , pp. 79-92
    • Narayanan, V.1    Pitchumani, V.2
  • 11
    • 0027871950 scopus 로고
    • Pipelined fault simulation on parallel machines using the circuit flow graph
    • S. E. Tai and D. Bhattacharya, "Pipelined fault simulation on parallel machines using the circuit flow graph," in Proc. IEEE Conf. Comput. Design, 1993, pp. 564-567.
    • (1993) Proc. IEEE Conf. Comput. Design , pp. 564-567
    • Tai, S.E.1    Bhattacharya, D.2
  • 13
    • 0025472561 scopus 로고
    • Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor
    • Aug.
    • N. Ishiura, M. Ito, and S. Yajima, "Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor," IEEE Trans. Computer-Aided Design, vol. 9, pp. 868-875, Aug. 1990.
    • (1990) IEEE Trans. Computer-Aided Design , vol.9 , pp. 868-875
    • Ishiura, N.1    Ito, M.2    Yajima, S.3
  • 14
    • 0026398793 scopus 로고
    • Performance trade-offs in a parallel test generation/fault simulation environment
    • Dec.
    • S. Patil and P. Banerjee, "Performance trade-offs in a parallel test generation/fault simulation environment," IEEE Trans. Computer-Aided Design, vol. 10, pp. 1542-1558, Dec. 1991.
    • (1991) IEEE Trans. Computer-Aided Design , vol.10 , pp. 1542-1558
    • Patil, S.1    Banerjee, P.2
  • 16
  • 18
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    • Method of fault simulation based on stem regions
    • F. Maamari and J. Rajski, "Method of fault simulation based on stem regions," IEEE Trans. Computer-Aided Design, vol. 9, pp. 212-220, 1990.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.