Resilience analysis: Tightening the CRPD bound for set-associative caches

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn , Issue , 2010, Pages 153-162

  Altmeyer, Sebastian ^a   Maiza, Claire ^a   Reineke, Jan ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

cache related preemption delay; lru caches; timing analysis

Indexed keywords

CACHE MISS; LOWER BOUNDS; MEMORY ACCESS; MEMORY BLOCKS; NEW APPROACHES; SCHEDULING ANALYSIS; SET-ASSOCIATIVE CACHES; TIGHT BOUND; TIMING ANALYSIS; UPPER BOUND; WORST-CASE EXECUTION TIME;

COST BENEFIT ANALYSIS; EMBEDDED SYSTEMS; LINGUISTICS; PROGRAM COMPILERS; REAL TIME SYSTEMS; TIME MEASUREMENT;

CACHE MEMORY;

EID: 77954489430     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1755888.1755911     Document Type: Conference Paper

References (19)

1. Mälardalen WCET benchmark suite. http://www.mrtc.mdh.se/projects/ wcet/benchmarks.html.
2. Papabench: a free real-time benchmark. http://www.irit.fr/recherches/ ARCHI/MARCH/rubrique.php3?id-rubrique=97.
3. B. Ackland, D. Anesko, D. Brinthaupt, S. J. Daubert, A. Kalavade, J. Knoblock, E. Micca, M. Moturi, C. J. Nicol, J. H. O'Neill, J. Othmer, E. Sackinger, K. J. Singh, J. Sweet, C. J. Terman, and J.Williams. A single-chip, 1.6 billion, 16-b mac/s multiprocessor dsp,. IEEE Journal of Solid-state circuits, 35(3):412-423, 2000.
4. S. Altmeyer and C. Burguière. A new notion of useful cache block to improve the bounds of cache-related preemption delay. In ECRTS '09, pages 109-118. IEEE Computer Society, 2009.
5. C. Ballabriga, H. Cassé, and P. Sainrat. An improved approach for set-associative instruction cache partial analysis. In SAC '08, pages 360-367, 2008.
6. C. Burguière, J. Reineke, and S. Altmeyer. Cache-related preemption delay computation for set-associative caches: Pitfalls and solutions. In WCET '09, 2009.
7. C. Ferdinand and R. Wilhelm. Fast and efficient cache behavior prediction for real-time systems. Real-Time Systems, 17(2/3):131-181, 1999.
8. C.-G. Lee, J. Hahn, S. L. Min, R. Ha, S. Hong, C. Y. Park, M. Lee, and C. S. Kim. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In RTSS'96, page 264. IEEE Computer Society, 1996.
9. T. Lundqvist and P. Stenström. Timing anomalies in dynamically scheduled microprocessors. In RTSS '99, page 12. IEEE Computer Society, 1999.
10. H. S. Negi, T. Mitra, and A. Roychoudhury. Accurate estimation of cache-related preemption delay. In CODES+ISSS'03. ACM, 2003.
11. F. Nemer, H. Cassé, P. Sainrat, J. P. Bahsoun, and M. D. Michiel. Papabench: a free real-time benchmark. In WCET '06, Dagstuhl, 2006.
12. F. Nemer, H. Cassé, P. Sainrat, and J. P. Bahsoun. Inter-task WCET computation for a-way instruction caches. In SIES '08, pages 169-176, 2008.
13. A. Rakib, O. Parshin, S. Thesing, and R. Wilhelm. Component-wise i-cache behavior prediction. In ATVA '04, pages 211-229, 2004.
14. J. Reineke and D. Grund. Relative competitive analysis of cache replacement policies. In LCTES'08, pages 51-60. ACM, June 2008.
15. J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian, J. Eisinger, and B. Becker. A definition and classification of timing anomalies. In WCET '06, Dagstuhl, 2006.
16. J. Staschulat and R. Ernst. Multiple process execution in cache related preemption delay analysis. In EMSOFT '04, pages 278-286. ACM, 2004.
17. J. Staschulat and R. Ernst. Scalable precision cache analysis for real-time software. ACM TECS, 6(4):25, 2007. ISSN 1539-9087.
18. Y. Tan and V. Mooney. Integrated intra- and inter-task cache analysis for preemptive multi-tasking real-time systems. In SCOPES'04, pages 182-199, 2004.
19. H. Tomiyama and N. D. Dutt. Program path analysis to bound cache-related preemption delay in preemptive real-time systems. In CODES '00. ACM, 2000.