A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2010, Pages 311-316

  Bartolini, Andrea ^a   Cacciari, Matteo ^a   Tilli, Andrea ^a   Benini, Luca ^a   Gries, Matthias ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b INTEL CORPORATION   (United States)

Author keywords

control system; multicore; resource managment

Indexed keywords

CHIP FAILURES; CLOSED-LOOP; CONTROL STRATEGIES; COSIMULATION; FAST PROTOTYPING; HARDWARE PLATFORM; HIGH POWER DENSITY; HOTSPOTS; MATLAB /SIMULINK; MULTI CORE; MULTI-CORE PROCESSOR; NONUNIFORM; ONLINE TUNING; POWER CONSUMPTION; RELIABILITY MANAGEMENT; SYSTEM SIMULATOR; TRACE DRIVEN SIMULATION; VIRTUAL PLATFORM;

CONTROL SYSTEMS; FUZZY CONTROL; INDUSTRIAL MANAGEMENT; LAKES; OBSERVABILITY;

RELIABILITY;

EID: 77954467009     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785553     Document Type: Conference Paper

References (21)

1. Argollo E. et al. COTSon: Infrastructure for full system simulation. In ACM SIGOPS Operating System Reviews, Jan 2009
2. Atienza D. et al. A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. Design Automation Conference (DAC), pages 618-623, 2006. (Pubitemid 47113970)
3. Benini L. et al. MPARM: Exploring the multi-processor SoC design space with SystemC. The Journal of VLSI Signal Processing, 41:169-182, Sep. 2005. (Pubitemid 40997653)
4. Brooks David et al. Wattch: a framework for architectural-level power analysis and optimizations. SIGARCH Comput. Archit. News, 28(2):83-94, 2000.
5. Hamann H. F. et al. Hotspot-limited microprocessors: Direct temperature and power distribution measurements. IEEE Journal of Solid-State Circuits, 42:56-65, Jan. 2007.
6. Hanson H. et al. Thermal response to DVFS: analysis with an Intel® Pentium® m. In ISLPED '07, pages 219-224, 2007. (Pubitemid 350239929)
7. Huang Wei et al. Accurate, pre-RTL temperature-aware design using a parameterized, geometric thermal model. IEEE Trans. Comput., 57(9):1277-1288, 2008.
8. Martin Milo M. K. et al. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News, 33(4):92-99, 2005.
9. N. Sakran et al. The implementation of the 65nm dual-core 64b merom processor. In IEEE International Solid-State Circuits Conference, 2007.
10. Nathan L. Binkert et al. The m5 simulator: Modeling networked systems. IEEE Micro, 26:52-60, 2006.
11. P Chaparro et al. Understanding the thermal implications of multi-core architectures. IEEE Transactions on Parallel and Distributed Systems,18(8):1055-1065, Aug. 2007.
12. Paci G. et al. Exploring "temperature-aware" design in low-power MPSoCs. In DATE '06, pages 838-843, 2006.
13. Thoziyoor Shyamkumar et al. A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies. ISCA '08, pages 51-62, 2008.
14. Tiwari A. et al. Facelift: Hiding and slowing down aging in multicores. MICRO '08, pages 129-140, 2008.
15. Intel Corporation. Intel® 64 and IA-32 Architectures Software Developer's Manual - Volume 3B, June 2009.
16. Intel Corporation. Intel® Xeon® Processor 7200 Series and 7300 Series Datasheet- Datasheet, September 2008.
17. ACPI Advanced Configuration and Power Interface Specification http://www.Intel.com/products/processor/manuals/
18. IDC. Worldwide server power and cooling expense 2006, 2010 forecast. http://www.sun.com/service/eco/IDCWorldwideServerPower-Consumption.pdf.
19. Intel Corporation. Intel Corporation. Intel® turbo boost technology in Intel® core™ microarchitecture (Nehalem) based processors. Technical report, 2008.
20. The MathWorks. MATLAB & Simulink. http://www.mathworks.com/.
21. Virtutech. Virtutech Simics. http://www.virtutech.com/.