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Volumn , Issue , 2010, Pages 47-52

A placement tool for a NoC-based dynamically reconfigurable system

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATED TOOL; DESIGN INFORMATION; DESIGN METHODOLOGY; DYNAMICALLY RECONFIGURABLE SYSTEMS; NETWORK ON CHIP; PARTIAL RECONFIGURATION; PLACEMENT ALGORITHM; PLACEMENT TOOLS; PROGRAMMABLE GATE; RE-CONFIGURABLE; STRUCTURED COMMUNICATION;

EID: 77954450667     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SPL.2010.5483005     Document Type: Conference Paper
Times cited : (5)

References (14)
  • 1
    • 0029754038 scopus 로고    scopus 로고
    • Run time reconfiguration: A method for enhancing the functional density of SRAM based fpgas
    • Jan.
    • J. Eldredge and B. Hutchings, "Run time reconfiguration: A method for enhancing the functional density of sram based fpgas," The Journal of VLSI Signal Processing, vol. 12, no. 1, pp. 67-86, Jan. 1996.
    • (1996) The Journal of VLSI Signal Processing , vol.12 , Issue.1 , pp. 67-86
    • Eldredge, J.1    Hutchings, B.2
  • 6
    • 60049093242 scopus 로고    scopus 로고
    • Cunoc: A dynamic scalable communication structure for dynamically reconfigurable fpgas
    • Aug.
    • S. Jovanovic, C. Tanougast, C. Bobda, and S. Weber, "Cunoc: A dynamic scalable communication structure for dynamically reconfigurable fpgas," Microprocessors and Microsystems, vol. 33, no. 1, pp. 24 - 36, Aug. 2009.
    • (2009) Microprocessors and Microsystems , vol.33 , Issue.1 , pp. 24-36
    • Jovanovic, S.1    Tanougast, C.2    Bobda, C.3    Weber, S.4
  • 7
    • 0035338121 scopus 로고    scopus 로고
    • Optimization of dynamic hardware reconfigurations
    • DOI 10.1023/A:1011188411132
    • J. Teich, S. Fekete, and J. Schepers, "Optimization of dynamic hardware reconfigurations," The Journal of Supercomputing, vol. 19, no. 1, pp. 57 - 75, May 2001. (Pubitemid 32471696)
    • (2001) Journal of Supercomputing , vol.19 , Issue.1 , pp. 57-75
    • Teich, J.1    Fekete, S.P.2    Schepers, J.3
  • 8
    • 84947932678 scopus 로고    scopus 로고
    • Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices
    • Field-Programmable Logic and Applications
    • A. Ahmadinia, C. Bobda, M. Bednara, and J. Teich, "A new approach for on-line placement on reconfigurable devices," Proceedings. 18th International Parallel and Distributed Processing Symposium, 2004. (Pubitemid 39210561)
    • (2004) LECTURE NOTES IN COMPUTER SCIENCE , Issue.3203 , pp. 847-851
    • Ahmadinia, A.1    Bobda, C.2    Fekete, S.P.3    Teich, J.4    Van Der Veen, J.C.5
  • 9
    • 34147144205 scopus 로고    scopus 로고
    • Optimal free-space management and routing-conscious dynamic placement for reconfigurable devices
    • DOI 10.1109/TC.2007.1028
    • A. Ahmadinia, C. Bobda, S. Fekete, J. Teich, and J. van der Veen, "Optimal free-space management and routing-conscious dynamic placement for reconfigurable devices," IEEE Transactions on Computers, vol. 56, no. 5, pp. 673 - 680, May 2007. (Pubitemid 46566210)
    • (2007) IEEE Transactions on Computers , vol.56 , Issue.5 , pp. 673-680
    • Ahmadinia, A.1    Bobda, C.2    Fekete, S.P.3    Teich, J.4    Van Der Veen, J.C.5
  • 12
    • 9544237156 scopus 로고    scopus 로고
    • Hermes: An infrastructure for low area overhead packet-switching networks on chip
    • F. Moraes, N. Calazans, A. Mello, L. Mller, and L. Ost, "Hermes: an infrastructure for low area overhead packet-switching networks on chip," Integration, the VLSI Journal, vol. 38, no. 1, pp. 69 - 93, 2004.
    • (2004) Integration, the VLSI Journal , vol.38 , Issue.1 , pp. 69-93
    • Moraes, F.1    Calazans, N.2    Mello, A.3    Mller, L.4    Ost, L.5
  • 14


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.