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Volumn , Issue , 2006, Pages 1113-1116

Design techniques for very high speed digital delta-sigma modulators aimed at all-digital RF transmitters

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; DIGITAL ARITHMETIC; DIGITAL RADIO; DYNAMIC PROGRAMMING; MODULATION; SPEED; STANDARDS;

EID: 47349104317     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2006.379634     Document Type: Conference Paper
Times cited : (10)

References (13)
  • 3
    • 47349113652 scopus 로고    scopus 로고
    • ETSI, Universal mobile telecommunications system (UMTS): UE radio transmission and reception (FDD), Technical Specification 125 101 v7.2.0, 2005.
    • ETSI, "Universal mobile telecommunications system (UMTS): UE radio transmission and reception (FDD)," Technical Specification 125 101 v7.2.0, 2005.
  • 4
    • 47349098577 scopus 로고    scopus 로고
    • J. Tao, T. Long, and S. I. Long, High efficiency switch mode amplifiers for mobile and base station applications, Final Report for MICRO Project, Department of Electrical and Computer Engineering, University of California, Santa Barbara, 2000-2001.
    • J. Tao, T. Long, and S. I. Long, "High efficiency switch mode amplifiers for mobile and base station applications," Final Report for MICRO Project, Department of Electrical and Computer Engineering, University of California, Santa Barbara, 2000-2001.
  • 6
    • 26844456361 scopus 로고    scopus 로고
    • Fundamentals of digital quadrature modulation
    • Feb
    • K. Gentile, "Fundamentals of digital quadrature modulation," in RF Design, Feb. 2003.
    • (2003) RF Design
    • Gentile, K.1
  • 8
    • 0030264539 scopus 로고    scopus 로고
    • C. Nagendra, M. J. Irwin, and R. M. Owens, Area-time-power tradeoffs in parallel adders, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], 43, pp. 689-702, 1996.
    • C. Nagendra, M. J. Irwin, and R. M. Owens, "Area-time-power tradeoffs in parallel adders," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], vol. 43, pp. 689-702, 1996.
  • 10
    • 0026867592 scopus 로고    scopus 로고
    • H. R. Srinivas and K. K. Parhi, A fast VLSI adder architecture, Solid-State Circuits, IEEE Journal of, 27, pp. 761-767, 1992.
    • H. R. Srinivas and K. K. Parhi, "A fast VLSI adder architecture," Solid-State Circuits, IEEE Journal of, vol. 27, pp. 761-767, 1992.
  • 12
    • 47349093663 scopus 로고    scopus 로고
    • Procédé de traitement d'un signal numérique au sein d'un modulateur delta-sigma, et modulateur delta-sigma numérique correspondant
    • patent pending
    • A. Frappé, A. Kaiser, and A. Cathelin, "Procédé de traitement d'un signal numérique au sein d'un modulateur delta-sigma, et modulateur delta-sigma numérique correspondant," patent pending, 2006.
    • (2006)
    • Frappé, A.1    Kaiser, A.2    Cathelin, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.