Modeling of stress-retarded thermal oxidation of nonplanar silicon structures for realization of nanoscale devices

IEEE Electron Device Letters

Volumn 31, Issue 7, 2010, Pages 719-721

  Ma, Fa Jun ^a,b   Rustagi, Subhash C ^a,c   Samudra, Ganesh S ^b   Zhao, Hui ^a,b   Singh, Navab ^a   Lo, Guo Qiang ^a   Kwong, Dim Lee ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c SILTERRA MALAYSIA SDN BHD   (Malaysia)

Author keywords

2 D oxidation; Nanowire (NW); orientation dependence; self limiting; shape engineering; stress retardation

Indexed keywords

2-D OXIDATION; ACCURATE MODELING; DRY OXYGEN; INITIAL OXIDATION; NANOSCALE DEVICE; NEW MODEL; NEW PARAMETERS; ORIENTATION DEPENDENCE; OXIDE THICKNESS; PARAMETER SET; SELF-LIMITING; SHAPE ENGINEERING; SILICON NANOWIRES; SILICON STRUCTURES; THERMAL OXIDATION;

NANOWIRES; OXYGEN;

OXIDATION;

EID: 77954142532     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2047375     Document Type: Article

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