Test pattern dependent FPGA based system architecture for JTAG tests

5th International Conference on Systems, ICONS 2010

Volumn , Issue , 2010, Pages 99-104

  Ostendorff, Steffen ^a   Wuttke, Heinz Dietrich ^a   Sachße, Jörg ^a   Escobar, Jorge Hernán Meza ^a  

^a ILMENAU UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Adaptive systems; Automatic test equipment; Boundary scan testing; Field programmable gate arrays

Indexed keywords

AUTOMATIC TEST EQUIPMENT; BOUNDARY SCAN; BOUNDARY-SCAN TESTING; LAYER CONCEPT; NEW APPROACHES; PROGRAMMABLE LOGIC; SELECTED EXAMPLES; SPEED-UPS; SYSTEM ARCHITECTURES; TEST PATTERN;

ADAPTIVE SYSTEMS; AUTOMATIC TESTING; LOGIC GATES; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE;

MOTIVATION;

EID: 77953731480     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICONS.2010.25     Document Type: Conference Paper

References (10)

1. th IEEE Latin America Test Workshop, Rio de Janeiro, Brazil, March 2-5, 2009.
2. IEEE Std. 1149.1-2001, IEEE standard test access port and boundary-scan architecture, 2001.
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4. th IEEE European Test Symposium, Ajaccio, Corsica, France, May 23-26, 2004.
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7. S. Park, T. Kim, "A new IEEE 1149.1 boundary scan design for the detection of delay defects", Design, Automation and Test in Europe, Paris, France, March 27-30, 2000.
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10. A. Jutman, S. Devadze, I. Aleksejev, "BS2VHDL and other embedded techniques for boundary scan test acceleration", in press, Nordic Test Forum 2009, Stockholm, Sweden, December 1-2, 2009.