Fast extended test access via JTAG and FPGAs

Proceedings - International Test Conference

Volumn , Issue , 2009, Pages

  Devadze, Sergei ^a   Jutman, Artur ^b   Aleksejev, Igor ^a   Ubar, Raimund ^b  

^a Testonica Lab   (Estonia)

^b TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY SCAN; ELECTRONIC MANUFACTURING; IN-SYSTEM PROGRAMMING; MANUFACTURING DEFECTS; PROGRAMMABLE DEVICES; SOFTWARE SUPPORT; SYSTEM LEVELS; TEST ACCESS; TEST ACCESS MECHANISM;

DATA TRANSFER; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLASH MEMORY; LOGIC DEVICES; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; PRINTED CIRCUIT TESTING;

TESTING;

EID: 76549083628     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2009.5355668     Document Type: Conference Paper

References (13)

1. K.P. Parker. The Boundary-Scan Handbook. Kluwer Academic Publishers, Boston, MA, USA, 2003, 373 p.
2. IEEE Std. 1149.1-2001, IEEE Standard test access port and boundary-scan architecture, 2001.
3. B. Nadeau-Dostie, et.al, "An Embedded Technique for At- Speed Interconnect Testing," in Proc. Int. Test Conf, Atlantic City, USA, Sept 28-30, 1999, pp.431-438.
4. th IEEE European Test Symposium, France, 2004, pp. 2-7.
5. H. Ehrenberg, Bob Russell, B. Van Treuren, "IEEE P1581 - Getting More Board Test Out of Boundary Scan", in Proc. Int. Test Conference (ITC'06), Santa Clara, USA, Oct 22-27, 2006, pp. 1-10.
6. B. Eklow, C. Barnhart, M. Ricchetti, T. Borroz, "IEEE 1149.6 - a practical perspective", In Proc. Int. Test Conference (ITC'03), Charlotte, NC, USA, Sep 30-Oct 2, 2003, pp. 70-78.
7. IEEE Std. 1149.6, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks, 2003.
8. D.A Bonnett, "Design for In-System Programming", in Proc. Int. Test Conference (ITC'99), Atlantic City, NJ, USA, Sept 28-30, 1999, pp. 252-259.
9. 256 Mbit Double Data Rate SDRAM Specification, (HYB25D2560160B datasheet), Infineon Technologies, Rev 1.2, 2004.
10. Virtex-4 Family Overview, Xilinx Inc., Rev. 4., 2008 http://www.xilinx. com/support/documentation/data-sheets/ds100.pdf
11. ML401/ML402/ML403 Evaluation Platform: User Guide, Xilinx Inc., 2006, 32 p.
12. 9-Mbit Pipelined Synchronous RAM Specification, ("CY7C1354B" datasheet), Cypress Semiconductor Corporation, http://download.cypress.com. edgesuite.net/design-resources/datasheets/contents/cy7c1354b-8.pdf
13. Intel StrataFlash® Memory (J3) http://www.intel.com/design/flcomp/ prodbref/298044.htm