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2009 10th Latin American Test Workshop, LATW 2009

Volumn , Issue , 2009, Pages

Turning JTAG inside out for fast extended test access

(4) Devadze, Sergei a Jutman, Artur a Aleksejev, Igor b Ubar, Raimund b

a estonica Lab OÜ (Estonia)

b TALLINN UNIVERSITY OF TECHNOLOGY (Estonia)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY SCAN; ELECTRONIC MANUFACTURING; IN-SYSTEM PROGRAMMING; MANUFACTURING DEFECTS; PROGRAMMABLE DEVICES; SOFTWARE SUPPORT; SYSTEM LEVELS; TEST ACCESS; TEST ACCESS MECHANISM;

DATA TRANSFER; FLASH MEMORY; LOGIC DEVICES; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; PRINTED CIRCUIT TESTING;

TESTING;

EID: 67649995868 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/LATW.2009.4813799 Document Type: Conference Paper

Times cited : (4)

References (11)

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- Kluwer Academic Publishers, Boston, MA, USA, 373 p
- K.P. Parker. The Boundary-Scan Handbook. Kluwer Academic Publishers, Boston, MA, USA, 2003, 373 p.
- (2003) The Boundary-Scan Handbook
- Parker, K.P.¹

2
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- IEEE Std. 1149.1-2001, IEEE Standard test access port and boundary-scan architecture, 2001.
- IEEE Std. 1149.1-2001, IEEE Standard test access port and boundary-scan architecture, 2001.

3
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- (1999) Proc. Int. Test Conf. (ITC'99) , pp. 431-438
- Nadeau-Dostie, B.¹

4
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- ̃At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults̃
- France
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- (2004) th IEEE European Test Symposium (ETS'04) , pp. 2-7
- Jutman, A.¹

5
- 39749118588
- ̃IEEE P1581-Getting More Board Test Out of Boundary Scañ
- Santa Clara, USA, Oct 22-27
- H. Ehrenberg, Bob Russell, B. Van Treuren, ̃IEEE P1581-Getting More Board Test Out of Boundary Scañ, in Proc. Int. Test Conference (ITC'06), Santa Clara, USA, Oct 22-27, 2006, pp. 1-10.
- (2006) Proc. Int. Test Conference (ITC'06) , pp. 1-10
- Ehrenberg, H.¹ Russell, B.² Van Treuren, B.³

6
- 63049131844
- ̃IEEE 1149.6-a practical perspectivẽ
- Charlotte, NC, USA, Sep 30-Oct 2
- B. Eklow, C. Barnhart, M. Ricchetti, T. Borroz, ̃IEEE 1149.6-a practical perspectivẽ, In Proc. Int. Test Conference (ITC'03), Charlotte, NC, USA, Sep 30-Oct 2, 2003, pp. 70-78.
- (2003) Proc. Int. Test Conference (ITC'03) , pp. 70-78
- Eklow, B.¹ Barnhart, C.² Ricchetti, M.³ Borroz, T.⁴

7
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- IEEE Std. 1149.6, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks, 2003.
- IEEE Std. 1149.6, IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks, 2003.

8
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- D.A Bonnett, ̃Design for In-System Programming̃, in Proc. Int. Test Conference (ITC'99), Atlantic City, NJ, USA, Sept 28-30, 1999, pp. 252-259.
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9
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- Virtex-5 Family Overview, Xilinx Inc., Rev. 4.4., 2008 http://www.xilinx.com/support/documentation/data-sheets/ds100.pdf
- (2008) Virtex-5 Family Overview, Xilinx Inc., Rev. 4.4

10
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- Virtex-5 FPGA Configuration User Guide, Xilinx Inc, Rev. 4.3, 2008. http://www.xilinx.com/support/documentation/virtex-5.htm
- (2008) Virtex-5 FPGA Configuration User Guide, Xilinx Inc, Rev. 4.3

11
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- 128Mb I-die SDRAM Specification K4S280432I, K4S280832I, K4S281632I, Synchronous DRAM datasheet, Samsung Electronics, Rev 1.1, 2006
- 128Mb I-die SDRAM Specification (K4S280432I, K4S280832I, K4S281632I), Synchronous DRAM datasheet, Samsung Electronics, Rev 1.1, 2006.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.