Exploration of hardware sharing for image encoders

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 1737-1742

  Lopez S ^a   Sarmiento, R ^a   Potter, P G ^b   Luk, W ^b   Cheung, P Y K ^b  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

FPGA; Hardware sharing; Image and video encoders; JPEG

Indexed keywords

COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SIGNAL ENCODING;

COMPUTATIONAL KERNELS; FEASIBLE SOLUTION; FUNCTIONAL BLOCK; HARDWARE SHARING; JPEG; NOVEL METHODOLOGY; THROUGHPUT CAPABILITY; VIDEO ENCODER;

IMAGE COMPRESSION;

EID: 77953107437     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457095     Document Type: Conference Paper

References (8)

1. B.M.H. Li and P.H.W. Leong, "Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors," Journal of Signal Processing Systems, vol. 51, no. 1, pp. 77-98, Apr. 2008.
2. F. Bensali and A. Amira, "Accelerating colour space conversion on reconfigurable hardware," Image and Vision Computing, vol. 23, no. 11, pp. 935-942, Oct. 2005.
3. E. Sahin and I. Hamzaoglu, "An efficient hardware architecture for H.264 intra predcition algorithm," in Proc. of DATE Conf., Apr. 2007, pp. 183-188.
4. A. Kulmala, T. D. Hamalainen and M. Hannikainen, "Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA," in Proc. Int. Conf. Field Programmable Logic and Appl., Aug. 2006, pp. 1-6.
5. L. Agostini, A.Azevedo, V. Rosa, E. Berriel, T. Santos, S. Bampi, and A.Susin, "FPGA Design of a H.264/AVC Main Profile Decoder for HDTV," in Proc. Int. Conf. Field Programmable Logic and Appl., Aug. 2006, pp. 1-6.
6. P. Potter, W. Luk, and P. Y. K. Cheung, "Partition-based exploration for reconfigurable JPEG designs", in Proc. DATE Conf., Apr. 2009, pp. 886-889.
7. T. Becker, W. Luk and P. Y. K. Cheung, "Parametric Design for Reconfigurable Software-Defined Radio," in Proc. of ARC, LNCS 5453, March 2009, pp. 15-26.
8. "Virtex-5 FPGA XtremeDSP design consideration," User Guide.[Online]