Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 429-434

  Alorda, B ^a   Torrens, G ^a   Bota, S ^a   Segura, J ^a  

^a UNIVERSITAT DE LES ILLES BALEARS   (Spain)

Author keywords

Critical charge; Nanometre SRAM; Static noise margin

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; CYTOLOGY; STATIC RANDOM ACCESS STORAGE;

65NM CMOS TECHNOLOGY; CRITICAL CHARGE; DESIGN RESTRICTION; IMPROVEMENT TECHNIQUE; NANOMETER TECHNOLOGY; NANOMETRES; STABILITY IMPROVEMENT; STATIC NOISE MARGIN;

INTEGRATED CIRCUIT DESIGN;

EID: 77953106745     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5457165     Document Type: Conference Paper

References (11)

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