Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and implantBench workloads

ISPASS 2010 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2010, Pages 33-44

  Ganesan, Karthik ^a   Jo, Jungho ^a   John, Lizy K ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE ERRORS; BURSTINESS; COMPUTER ARCHITECTS; CORRELATION COEFFICIENT; DESIGN CHANGE; DYNAMIC INSTRUCTIONS; INSTRUCTION PER CYCLES; MAIN MEMORY; MEMORY LEVEL PARALLELISMS; MICRO ARCHITECTURES; MICRO-ARCHITECTURE DESIGN; POWER CHARACTERISTIC; POWER CONSUMPTION; SILICON DESIGN; SIMULATION TIME; SYNTHETIC BENCHMARK; TARGET APPLICATION;

BENCHMARKING; COMPUTER SIMULATION; COMPUTER SOFTWARE;

DESIGN;

EID: 77952570824     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2010.5452076     Document Type: Conference Paper

References (22)

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