Automatic testcase synthesis and performance model validation for high-performance PowerPC processors

ISPASS 2006: IEEE International Symposium on Performance Analysis of Systems and Software, 2006

Volumn 2006, Issue , 2006, Pages 154-165

  Bell Jr , Robert H ^a,b   Bhatia, Rajiv R ^a,b   John, Lizy K ^b   Stuecheli, Jeff ^a,b   Griswell, John ^a   Tu, Paul ^a   Capps, Louis ^a   Blanchard, Anton ^a   Thai, Ravel ^b  

^a IBM   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTCASE SYNTHESIS; PERFORMANCE MODEL; POWERPC PROCESSORS;

AUTOMATIC PROGRAMMING; BANDWIDTH; CONTROL SYSTEM SYNTHESIS; MATHEMATICAL MODELS; PROGRAM COMPILERS;

PROGRAM PROCESSORS;

EID: 33750806476     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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