High speed six-transistor static random access memory cells using single grain thin film transistors fabricated at low temperature process

Japanese Journal of Applied Physics

Volumn 49, Issue 3 PART 2, 2010, Pages

  Golshani, Negin ^a   Derakhshandeh, Jaber ^a   Ishihara, Ryoichi ^a   Beenakker, Cees I M ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; ANALYTICAL CALCULATION; CZOCHRALSKI PROCESS; EXCIMER LASER CRYSTALLIZATION; GATE LENGTH; GRAIN FILTERS; LOW-TEMPERATURE PROCESS; POWER SUPPLY; SINGLE GRAINS; SINGLE-GRAIN THIN-FILM TRANSISTOR; SRAM CELL; STATIC NOISE MARGIN; STATIC RANDOM ACCESS MEMORY; TRANSIENT SIMULATION;

EXCIMER LASERS; FABRICATION; GAS LASERS; HEAT RADIATION; THIN FILM TRANSISTORS; THIN FILMS;

STATIC RANDOM ACCESS STORAGE;

EID: 77952564113     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.49.03CA09     Document Type: Article

References (11)

1. H. Ebihara, N. Karaki, T. Kodaira, S. Hirabayashi, S. Inoue, and T. Shimoda: SID Int. Symp. Dig. Tech. Pap. 37 (2006) 339.
2. R. Ishihara, V. Rana, M. He, Y. Hiroshima, S. Inoue, W. Metselaar, and K. Beenakker: Solid-State Electron. 52 (2008) 353.
3. R. Ishihara, Y. Hiroshima, D. Abe, B. D. Van Dijk, P. C. Van der Wilt, S. Higashi, S. Inoue, T. Shimoda, J. W. Metselaar, and C. I. M. Beenakker: IEEE Trans. Electron Devices 51 (2004) 500.
4. S. B. Park, Y. W. Kim, Y. G. Ko, K. I. Kim, I. K. Kim, H.-S. Kang, J. O. Yu, and K. P. Suh: IEEE J. Solid-State Circuits 34 (1999) 1436.
5. J. B. Kuang, S. Ratanaphanyarat, M. J. Saccamango, L. L. C. Hsu, R. C. Flaker, L. F. Wagner, S. F. S. Chu, and G. G. Shahidi: IEEE J. Solid-State Circuits 32 (1997) 837.
6. N. Saputra, M. Danesh, A. Baiano, R. Ishihara, J. R. Long, N. Karaki, and S. Inoue: IEEE J. Solid-State Circuits 43 (2008) 1563.
7. M. He, R. Ishihara, Y. Hiroshima, S. Inoue, T. Shimoda, W. Metselaar, and K. Beenakker: Jpn. J. Appl. Phys. 45 (2006) 1.
8. K. Roy and S. Prasad: Low-Power CMOS VLSI Circuit Design (Wiley, New York, 2000).
9. A. Pavlov and M. Sachdev: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test (Springer, Heidelberg, 2008) Frontiers in Electronic Testing, Vol.40, Chap. 2, p. 17.
10. J. Derakhshandeh, M. R. Tajari Mofrad, R. Ishihara, and C. I. M. Beenakker: Proc. Device Research Conf., 2009.
11. A. Amara and O. Rozeau: Planar Double-Gate Transistor: From Technology to Circuit (Springer, Heidelberg, 2009) Vol.VIII, p. 212.