Modeling memory concurrency for multi-socket multi-core systems

ISPASS 2010 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2010, Pages 66-75

  Mandal, Anirban ^a   Fowler, Rob ^a   Porterfield, Allan ^a  

^a Renaissance Computing Institute   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LATENCY; COMMON MODELS; HARDWARE ARCHITECTURE; MEMORY ACCESS; MEMORY CONCURRENCY; MEMORY CONTROLLER; MEMORY LOAD; MEMORY PERFORMANCE; MEMORY REFERENCES; MEMORY SYSTEMS; MODELING PROCESS; MULTI CORE; MULTI-CORE SYSTEMS; PERFORMANCE PROBLEMS; PROCESSOR CHIPS; SUB-SYSTEMS;

BANDWIDTH; COMPUTER SOFTWARE; CONCURRENCY CONTROL; MICROPROCESSOR CHIPS; NANOTECHNOLOGY;

MATHEMATICAL MODELS;

EID: 77952562204     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2010.5452064     Document Type: Conference Paper

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