Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Murugesan, M ^a   Bea, J C ^a   Kino, H ^a   Ohara, Y ^a   Kojima, T ^a   Noriki, A ^a   Lee, K W ^a   Kiyoyama, K ^a   Fukushima, T ^a   Nohira, H ^b   Hattori, T ^a   Ikenaga, E ^c   Tanaka, T ^a   Koyanag, M ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b TOKYO CITY UNIVERSITY   (Japan)

^c JAPAN SYNCHROTRON RADIATION RESEARCH INSTITUTE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER GENERATION LIFETIMES; KEY PROCESS; LOCAL STRESS; LOW TEMPERATURES; LSI FABRICATION; MECHANICAL STRESS; METAL CONTAMINATION; MICRO RAMAN SPECTROSCOPY; MICRO-BUMPS; MOS TRANSISTORS; ON CURRENTS; SI SUBSTRATES; STRESS/STRAIN; THROUGH-SI VIA; WAFER THINNING; XPS;

CONTAMINATION; CRYSTAL DEFECTS; ELECTRON DEVICES; METALS; RAMAN SPECTROSCOPY; SEMICONDUCTING SILICON COMPOUNDS; SILICON; STRESSES; SUBSTRATES; THREE DIMENSIONAL; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; WAFER BONDING;

SILICON WAFERS;

EID: 77952391373     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424348     Document Type: Conference Paper

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