Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Ragnarsson, L A ^a   Li, Z ^a   Tseng, J ^a   Schram, T ^a   Rohr, E ^a   Cho, M J ^a   Kauerauf, T ^a   Conard, T ^a   Okuno, Y ^a   Parvais, B ^a   Absil, P ^a   Biesemans, S ^a   Hoffmann, T Y ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DRIVE CURRENTS; EFFECTIVE WORK FUNCTION; ELECTRODE OPTIMIZATION; GATE FIRST; GATE-LAST; HIGH-PERFORMANCE CMOS; INTEGRATION APPROACH; INTERFACE LAYER; NMOS DEVICES; PMOS DEVICES; POLY GATES; SIGE SOURCE/DRAIN; TDDB LIFETIME;

CUTOFF FREQUENCY; DIELECTRIC MATERIALS; ELECTRON DEVICES; HAFNIUM COMPOUNDS; OPTIMIZATION;

GATES (TRANSISTOR);

EID: 77952370427     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424254     Document Type: Conference Paper

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