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Volumn , Issue , 2008, Pages 141-150

Cell GC: Using the cell synergistic processor as a garbage collection coprocessor

Author keywords

Accelerator; BDW; Cell; Coprocessor; Explicitly managed memory hierarchies; Garbage collection; Local store; Mark sweep; SPE; SPU

Indexed keywords

CO-PROCESSORS; EXPLICITLY MANAGED MEMORY HIERARCHIES; GARBAGE COLLECTION; MARK-SWEEP; MEMORY HIERARCHY;

EID: 77952324044     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1346256.1346276     Document Type: Conference Paper
Times cited : (8)

References (20)
  • 5
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    • Scott Clark, Kent Haselhorst, Kerry Imming, John Irish, Dave Krolak, and Tolga Ozguner. Cell Broadband Engine interconnect and memory interface. In Hot Chips 17, Palo Alto, CA, August 2005.
    • (2005) Hot Chips , vol.17
    • Clark, S.1    Haselhorst, K.2    Imming, K.3    Irish, J.4    Krolak, D.5    Ozguner, T.6
  • 6
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    • Using advanced compiler technology to exploit the performance of the Cell Broadband Engine Architecture
    • Alexandre Eichenberger et al. Using advanced compiler technology to exploit the performance of the Cell Broadband Engine Architecture. IBM System Journal, 45(1), 2006.
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  • 9
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    • The cell broadband engine: Exploiting multiple levels of parallelism in a chip multiprocessor
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    • Michael Gschwind. The Cell Broadband Engine: Exploiting multiple levels of parallelism in a chip multiprocessor. International Journal of Parallel Programming, June 2007.
    • (2007) International Journal of Parallel Programming
    • Gschwind, M.1
  • 10
    • 34447296999 scopus 로고    scopus 로고
    • An open source environment for cell broadband engine system software
    • June
    • Michael Gschwind, David Erb, Sid Manning, and Mark Nutter. An open source environment for cell broadband engine system software. IEEE Computer, June 2007.
    • (2007) IEEE Computer
    • Gschwind, M.1    Erb, D.2    Manning, S.3    Nutter, M.4
  • 11
    • 33746772128 scopus 로고    scopus 로고
    • A novel SIMD architecture for the CELL heterogeneous chip-multiprocessor
    • Palo Alto, CA, August
    • Michael Gschwind, Peter Hofstee, Brian Flachs, Martin Hopkins, Yukio Watanabe, and Takeshi Yamazaki. A novel SIMD architecture for the CELL heterogeneous chip-multiprocessor. In Hot Chips 17, Palo Alto, CA, August 2005.
    • (2005) Hot Chips , vol.17
    • Gschwind, M.1    Hofstee, P.2    Flachs, B.3    Hopkins, M.4    Watanabe, Y.5    Yamazaki, T.6
  • 14
    • 0032058458 scopus 로고    scopus 로고
    • Informing memory operations: Memory performance feedback mechanisms and their applications
    • May
    • Mark Horowitz, Margaret Martonosi, Todd C. Mowry, and Michael D. Smith. Informing memory operations: memory performance feedback mechanisms and their applications. ACM Transactions on Computer Systems (TOCS), 16(2):170-205, May 1998.
    • (1998) ACM Transactions on Computer Systems (TOCS) , vol.16 , Issue.2 , pp. 170-205
    • Horowitz, M.1    Martonosi, M.2    Mowry, T.C.3    Smith, M.D.4
  • 15
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    • Performance insights on executing non-graphics applications on CUDA on the NVIDIA GeForce 8800 GTX
    • Palo Alto, CA
    • Wen-mei Hwu et al. Performance insights on executing non-graphics applications on CUDA on the NVIDIA GeForce 8800 GTX. In Hot Chips 19, Palo Alto, CA, 2007.
    • (2007) Hot Chips , vol.19
    • Hwu, W.-M.1
  • 18
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    • CellVM: A homogeneous virtual machine runtime system for a heterogeneous single-chip multiprocessor
    • School of Information and Computer Science, University of California, Irvine, November
    • Albert Noll, Andreas Gal, and Michael Franz. CellVM: A homogeneous virtual machine runtime system for a heterogeneous single-chip multiprocessor. Technical report, School of Information and Computer Science, University of California, Irvine, November 2006.
    • (2006) Technical Report
    • Noll, A.1    Gal, A.2    Franz, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.