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Volumn 16, Issue 2, 1998, Pages 170-205

Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications

Author keywords

Cache miss notification; Design; Experimentation; Memory latency; Performance; Processor architecture

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; COMPUTER SOFTWARE; FEEDBACK CONTROL; OPTIMIZATION;

EID: 0032058458     PISSN: 07342071     EISSN: None     Source Type: Journal    
DOI: 10.1145/279227.279230     Document Type: Article
Times cited : (19)

References (47)
  • 3
    • 84945714902 scopus 로고
    • Sparcle: An evolutionary processor design for large-scale multiprocessors
    • AGARWAL, A., KUBIATOWICZ, J., AND KRANZ, D. 1993. Sparcle: An evolutionary processor design for large-scale multiprocessors. IEEE Micro 13, 48-61.
    • (1993) IEEE Micro , vol.13 , pp. 48-61
    • Agarwal, A.1    Kubiatowicz, J.2    Kranz, D.3
  • 8
    • 0024665985 scopus 로고
    • Performance-measurement tools in a multiprocessor environment
    • BURKHART, H. AND MILLEN, R. 1989. Performance-measurement tools in a multiprocessor environment. IEEE Trans. Comput. 38, 5 (May), 725-737.
    • (1989) IEEE Trans. Comput. , vol.38 , Issue.5 MAY , pp. 725-737
    • Burkhart, H.1    Millen, R.2
  • 10
    • 0027574855 scopus 로고
    • A methodology for procedure cloning
    • COOPER, K., HALL, M., AND KENNEDY, K. 1993. A methodology for procedure cloning. Comput. Lang. 19, 2 (Apr.).
    • (1993) Comput. Lang. , vol.19 , Issue.2 APR
    • Cooper, K.1    Hall, M.2    Kennedy, K.3
  • 14
    • 0026821098 scopus 로고
    • New CPU benchmark suites from SPEC
    • (San Francisco, CA, Feb. 24-28, 1992). IEEE Computer Society Press, Los Alamitos, CA
    • DIXIT, K. M. 1992. New CPU benchmark suites from SPEC. In Proceedings of 37th International Conference on Computer Communications (San Francisco, CA, Feb. 24-28, 1992). IEEE Computer Society Press, Los Alamitos, CA, 305-310.
    • (1992) Proceedings of 37th International Conference on Computer Communications , pp. 305-310
    • Dixit, K.M.1
  • 15
    • 0025441653 scopus 로고
    • A tool to aid in the design, implementation, and understanding of matrix algorithms for parallel processors
    • DONGARRA, J. J., BREWER, O., KOHL, J. A., AND FINEBERG, S. 1990. A tool to aid in the design, implementation, and understanding of matrix algorithms for parallel processors. J. Parallel Distrib. Comput. 9, 2 (June), 185-202.
    • (1990) J. Parallel Distrib. Comput. , vol.9 , Issue.2 JUNE , pp. 185-202
    • Dongarra, J.J.1    Brewer, O.2    Kohl, J.A.3    Fineberg, S.4
  • 17
    • 0028261367 scopus 로고
    • Complexity/performance tradeoffs with non-blocking loads
    • (Chicago, Ill., April 18-21, 1994). IEEE Computer Society Press, Los Alamitos, CA
    • FARKAS, K. AND JOUPPI, N. 1994. Complexity/performance tradeoffs with non-blocking loads. In Proceedings of the 21st International Symposium on Computer Architecture (Chicago, Ill., April 18-21, 1994). IEEE Computer Society Press, Los Alamitos, CA, 211-222.
    • (1994) Proceedings of the 21st International Symposium on Computer Architecture , pp. 211-222
    • Farkas, K.1    Jouppi, N.2
  • 18
    • 0019596071 scopus 로고
    • Trace scheduling: A technique for global microcode compaction
    • FISHER, J. 1981. Trace scheduling: A technique for global microcode compaction. IEEE Trans. Comput. C-30, 7 (July), 478-490.
    • (1981) IEEE Trans. Comput. , vol.C-30 , Issue.7 JULY , pp. 478-490
    • Fisher, J.1
  • 20
    • 0027242764 scopus 로고
    • Mtool: An integrated system for performance debugging shared memory multiprocessor applications
    • GOLDBERG, A. J. AND HENNESSY, J. L. 1993. Mtool: An integrated system for performance debugging shared memory multiprocessor applications. IEEE Trans. Parallel Distrib. Syst. 4, 1 (Jan.), 28-40.
    • (1993) IEEE Trans. Parallel Distrib. Syst. , vol.4 , Issue.1 JAN , pp. 28-40
    • Goldberg, A.J.1    Hennessy, J.L.2
  • 24
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • JOUPPI, N. 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th International Symposium on Computer Architecture.
    • (1990) Proceedings of the 17th International Symposium on Computer Architecture
    • Jouppi, N.1
  • 27
    • 0028517833 scopus 로고
    • Cache profiling and the SPEC benchmarks: A case study
    • LEBECK, A. R. AND WOOD, D. A. 1994. Cache profiling and the SPEC benchmarks: A case study. Computer 27, 10 (Oct.), 15-26.
    • (1994) Computer , vol.27 , Issue.10 OCT , pp. 15-26
    • Lebeck, A.R.1    Wood, D.A.2
  • 30
    • 0029290849 scopus 로고
    • Tuning memory performance in sequential and parallel programs
    • MARTONOSI, M., GUPTA, A., AND ANDERSON, T. 1995. Tuning memory performance in sequential and parallel programs. Computer 28, 4 (Apr.), 32-40.
    • (1995) Computer , vol.28 , Issue.4 APR , pp. 32-40
    • Martonosi, M.1    Gupta, A.2    Anderson, T.3
  • 31
    • 0004163531 scopus 로고
    • Pentium secrets
    • MATHISEN, T. 1994. Pentium secrets. BYTE 19, 7, 191-192.
    • (1994) BYTE , vol.19 , Issue.7 , pp. 191-192
    • Mathisen, T.1
  • 33
    • 0031357519 scopus 로고    scopus 로고
    • Predicting data cache misses in non-numeric applications through correlation profiling
    • MOWRY, T. C. AND LUK, C.-K. 1997. Predicting data cache misses in non-numeric applications through correlation profiling. In Proceedings of Micro-30.
    • (1997) Proceedings of Micro-30
    • Mowry, T.C.1    Luk, C.-K.2
  • 40
    • 0002255264 scopus 로고
    • SPLASH: Stanford parallel applications for shared-memory
    • SINGH, J. P., WEBER, W.-D., AND GUPTA, A. 1992. SPLASH: Stanford parallel applications for shared-memory. SIGARCH Comput. Archit. News 20, 1 (Mar.), 5-44.
    • (1992) SIGARCH Comput. Archit. News , vol.20 , Issue.1 MAR , pp. 5-44
    • Singh, J.P.1    Weber, W.-D.2    Gupta, A.3
  • 41
    • 0028288125 scopus 로고
    • Architectural support for performance tuning: A case study on the SPARCcenter 2000
    • (Chicago, Ill., April 18-21, 1994). IEEE Computer Society Press, Los Alamitos, CA
    • SINGHAL, A. AND GOLDBERG, A. J. 1994. Architectural support for performance tuning: A case study on the SPARCcenter 2000. In Proceedings of the 21st International Symposium on Computer Architecture (Chicago, Ill., April 18-21, 1994). IEEE Computer Society Press, Los Alamitos, CA, 48-59.
    • (1994) Proceedings of the 21st International Symposium on Computer Architecture , pp. 48-59
    • Singhal, A.1    Goldberg, A.J.2
  • 42
    • 0001558043 scopus 로고
    • Architecture and applications of the HEP Multiprocessor Computer System
    • SPIE Press, Bellingham, WA
    • SMITH, B. J. 1981. Architecture and applications of the HEP Multiprocessor Computer System. In SPIE Real-Time Signal Processing IV. SPIE Press, Bellingham, WA.
    • (1981) SPIE Real-Time Signal Processing IV
    • Smith, B.J.1
  • 47
    • 0030129806 scopus 로고    scopus 로고
    • The MIPS R10000 superscalar microprocessor
    • YEAGER, K. C. 1996. The MIPS R10000 superscalar microprocessor. IEEE Micro 16, 2 (Apr.), 28-40.
    • (1996) IEEE Micro , vol.16 , Issue.2 APR , pp. 28-40
    • Yeager, K.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.