Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications

ACM Transactions on Computer Systems

Volumn 16, Issue 2, 1998, Pages 170-205

  Horowitz, Mark ^a   Martonosi, Margaret ^b,e   Mowry, Todd C ^c,f   Smith, Michael D ^d  

^a STANFORD UNIVERSITY   (United States)

^b PRINCETON UNIVERSITY   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

^d HARVARD UNIVERSITY   (United States)

^e Princeton University   (United States)

^f Carnegie Mellon University   (United States)

Author keywords

Cache miss notification; Design; Experimentation; Memory latency; Performance; Processor architecture

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; COMPUTER SOFTWARE; FEEDBACK CONTROL; OPTIMIZATION;

CACHE MEMORIES; INFORMING MEMORY OPERATIONS;

STORAGE ALLOCATION (COMPUTER);

EID: 0032058458     PISSN: 07342071     EISSN: None     Source Type: Journal    
DOI: 10.1145/279227.279230     Document Type: Article

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